JEDEC JESD76-2-2001 Standard Description of 1 2 V CMOS Logic Devices (Normal Range Operations)《1 2 V CMOS逻辑设备的标准描述(常规范围运作)》.pdf

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1、JEDECSTANDARDStandard Description of 1.2 V CMOS LogicDevices (Normal Range Operations)JESD76-2JUNE 2001JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONNOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors level and subseque

2、ntly reviewed andapproved by the EIA General Counsel.JEDEC standards and publications are designed to serve the public interest througheliminating misunderstandings between manufacturers and purchasers, facilitatinginterchangeability and improvement of products, and assisting the purchaser in select

3、ing andobtaining with minimum delay the proper product for use by those other than JEDECmembers, whether the standard is to be used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not theiradoption may involve patents or articles, mate

4、rials, or processes. By such action JEDEC doesnot assume any liability to any patent owner, nor does it assume any obligation whatever toparties adopting the JEDEC standards or publications.The information included in JEDEC standards and publications represents a sound approachto product specificati

5、on and application, principally from the solid state device manufacturerviewpoint. Within the JEDEC organization there are procedures whereby an JEDEC standardor publication may be further processed and ultimately become an ANSI/EIA standard.No claims to be in conformance with this standard may be m

6、ade unless all requirementsstated in the standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard orpublication should be addressed to JEDEC Solid State Technology Association, 2500 WilsonBoulevard, Arlington, VA 22201-3834, (703)907-7560/7559 or www.jedec

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8、ial.PRICE: Please refer to the currentCatalog of JEDEC Engineering Standards and Publications or call Global EngineeringDocuments, USA and Canada (1-800-854-7179), International (303-397-7956)Printed in the U.S.A.All rights reservedPLEASE!DONT VIOLATETHELAW!This document is copyrighted by the Electr

9、onic Industries Alliance and may not bereproduced without permission.Organizations may obtain permission to reproduce a limited number of copiesthrough entering into a license agreement. For information, contact:JEDEC Solid State Technology Association2500 Wilson BoulevardArlington, Virginia 22201-3

10、834or call (703) 907-7559JEDEC Standard No. 76-2Page 1STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES(Normal Range Operations)(From JEDEC Board Ballot JCB-01-21, formulated under the cognizance of the JC-40 Committee onDigital Logic.)1ScopeThis standard defines dc interface, switching parameters an

11、d test loading for digital logic devicesbased on 1.2 V (normal range) power supply levels.The purpose is to provide a standard specification for uniformity, multiplicity of sources, eliminationof confusion, ease of device specification, and ease of use.2 Definitions for the purpose of this documentP

12、refixes “54” or “74” immediately preceding family name indicate the operating temperature range.For example, 54xxx refers to the Military (MIL) version of devices which are specified overtemperature range of 55 C to +125 C. 74xxx refers to the Commercial (COML) version of deviceswhich are specified

13、over 40 C to +85 C.3 Standard specifications3.1 Absolute maximum continuous ratings 1,2SYMBOL PARAMETER CONDITIONS RATING UNITVDDdc Supply voltage -0.5 to +1.8 VVINdc Input voltage (note 3) -0.5 to VDD+0.5 VVOUTdc Output voltage (note 3) Output in OFF state -0.5 to VDD+0.5 VTSTGStorage temperature -

14、65 to +150 CNOTE 1 Absolute maximum continuous ratings are those values beyond which damage to the device mayoccur. Exposure to these conditions or conditions beyond those indicated may adversely affectdevice reliability. Functional operation under these conditions is not implied.NOTE 2 Under transi

15、ent conditions these ratings may be exceeded as defined elsewhere in this specification.NOTE 3 Not to exceed 1.8 VJEDEC Standard No. 76-2Page 23 Standard specifications (contd)3.2 Recommended operating conditionsLIMITSSYMBOL PARAMETERMIN MAXUNITVDDdc Supply voltage (Normal Range) 1.1 1.3 VVINInput v

16、oltage 0 VDDVVOUTOutput voltage 0 VDDVTAMBOperating free-air temperature -40 +85 C3.3 DC specificationsOver recommended operating conditions. Voltages are referenced to GNDLIMITSSYMBOL PARAMETER TESTCONDITIONMIN MAX UNITVIHInput High Voltage 0.65VDDVDD+0.3 VVILInput Low Voltage -0.3 0.35 VDDVVOHOutp

17、ut High Voltage IOH= -100 A VDD-0.1 VVOHOutput High Voltage IOH= -2 mA 0.75 VDDVVOLOutput Low Voltage IOL= 100 A 0.1 VVOLOutput Low Voltage IOL= 2 mA 0.25 VDDVJEDEC Standard No. 76-2Page 34 Test circuit and switching waveformsMEASUREMENT 2. ENABLE AND DISABLE TIMEStWVDD/2VDD/2InputMEASUREMENT 3. PUL

18、SE DURATION (WIDTH)MEASUREMENTSVDD/2tsu thVDD/2VDD/2Timing InputData InputVDDVDD0 V0 VMEASUREMENT 4. SETUP AND HOLD TIMESTEST S1tpd OpentPLZ/tPZL 2 X VDDtPHZ/tPZH GNDOpenFrom OutputUnder TestCL = 15pF(see note 1)2k2k2 x VDDGNDtPLH tPHLVDD/2VDD/2VDD/2VDD/2InputOutputVDD0 VVOHVOLMEASUREMENT 1. PROPAGA

19、TION DELAY TIMESVOL + 0.1 VtPZHtPZLVDD/2 VDD/2VDD/2VDD/2tPHZVOH 0.1 VOutput ControlOutput Waveform 1S1 at 2 x VDD(see note 2)Output Waveform 2S1 at GND(see note 2)NOTE 1 CLincludes probe, and jig capacitance.NOTE 2 Waveform 1 is for an output with internal conditions such that the output is low exce

20、pt when disabled by theoutput control.NOTE 3 Waveform 2 is for an output with internal conditions such that the output is high except when disabled by theoutput control.NOTE 4 All input pulses are supplied by generators having the following characteristics:PRR 10 MHz, ZO= 50 , tr= tf 2 ns.NOTE 5 The outputs are measured one at a time with one transition per measurement.NOTE 6 tPLZand tPHZare the same as tdis.NOTE 7 tPZLand tPZHare the same as ten.NOTE 8 tPLHand tPHLare the same as tpd.tPLZS1