JEDEC JESD75-5-2004 SON QFN Package Pinouts Standardized for 1- 2- and 3-Bit Logic Functions《1 2和3位逻辑功能的SON QFN包装插脚引线标准化》.pdf

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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD75-5JULY 2004JEDECSTANDARDSON/QFN Package Pinouts Standardized for 1-, 2-, and 3-Bit Logic FunctionsNOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approvedthrough the JEDEC Council level and subsequently revie

2、wed and approved by the JEDEC Legal Counsel.JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purchaser in selecting and o

3、btaining with minimum delay theproper product for use by those other than JEDEC members, whether the standard is to be used eitherdomestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoption mayinvolve patents or articles, materials, or

4、 processes. By such action JEDEC does not assume any liability toany patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards orpublications.The information included in JEDEC standards and publications represents a sound approach to productspecification and ap

5、plication, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in thestandard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication shouldbe a

6、ddressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA22201-3834, (703)907-7559 or www.jedec.org.Published byJEDEC Solid State Technology Association 20042500 Wilson BoulevardArlington, VA 22201-3834This documentmay be downloaded free of charge, however JEDEC reta

7、ins the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material.Price: Please refer to the current Catalog of JEDEC Engineering Standards and Publications at www.jedec.orgPrinted in the U.S.A.All rights reservedPLEASE! DONT VIOLAT

8、E THE LAW! This document is copyrighted by the JEDEC Solid State Technology Association and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Tec

9、hnology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 75-5Page 1SON/QFN PACKAGE PINOUTS STANDARDIZED FOR 1-, 2-, AND 3-BIT LOGIC FUNCTIONS(From JEDEC Board Ballot JCB-04-44, formulated under the cognizance of the JC-40 Committee on Digital

10、 Logic.)1ScopeThis standard defines device pinout for 1-, 2- and 3-bit wide logic functions. This pinout specifically applies to the conversion of Dual-Inline-Packaged (DIP) 1-, 2- and 3-bit logic devices to SON/QFN packaged 1-, 2- and 3-bit logic devices. The purpose of this document is to provide

11、a pinout standard for 1-, 2- and 3-bit logic devices offered in 6- or 8-land SON/QFN packages for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.2 Terms and definitions (for the purpose of this document)DIP: Dual In-line Pin Package (gull

12、-wing)SOP: Small-Outline Package; 0.95-mm lead pitch; 1.6mm wide body (MO-178; variations AA (5-ld), AB (6-ld), and BA (8-ld).SSOP: Shrink Small-Outline Package; 0.65-mm lead pitch; 5.3-mm wide body (MO-150; variation AA (8-ld).TSSOP: Thin Shrink Small-Outline Package; 0.65-mm lead pitch; 4.4-mm wid

13、e body (MO-153; variation AA (8-ld).SON: Plastic Very Very Thin (P-WFDSON), Ultra Thin (P-UFDSON), and Extremely Thin (P-XFDSON), Fine Pitch Dual Small Outline Non- Leaded Package Family (MO-252 Issue A, variation UAAD (6-ld).QFN: Plastic Very Very Thin (P-WFQFN), Ultra Thin (P-UFQFN), and Extremely

14、 Thin (P-XFQFN), Fine Pitch Quad Flat Small Outline, Non-Leaded Package Family (MO-255 Issue A, variation UAAD (8-ld), variation UABD (10-ld).3Pinout sandard3.1 DescriptionThe following criteria shall be used to convert existing 1-, 2- and 3-bit logic device functions offered in 5-, 6- and 8-pin DIP

15、 packages (e.g., SOP, SSOP, TSSOP) to 1-, 2- and 3-bit logic device functions offered in the 6- and 8-land SON/QFN packages:a) Attributes for the SON (6-ld) and QFN (8-ld) package package shall be as follows:6-land, 0.5-mm land pitch with 1.0-mm 1.45-mm body size and 3-row 2-column land array.8-land

16、, 0.5-mm land pitch with 1.6-mm 1.6-mm body size and depopulated quad array.b) The pinout conversions shall be in accordance with the diagrams shown in sections 3.2 and 3.5. Each device shallbe pinned out based on its present package/pinout and the pinout tables in sections 3.3, 3.4, and 3.6.JEDEC S

17、tandard No. 75-5Page 23 Pinout standard (contd)3.2 6-land SON package (MO-252, variation UAAD)Figure 1 Pinout configuration - Bottom view3.3 Pin conversion from 5-pin DIP to 6-land SON packageThe pinout adopts the naming convention of logic devices in 5-pin DIP packages. The signal nomenclature used

18、 in this table is intended to define the functionality of each pin and not require that a specific naming convention be followed. Each product vendor is free to name the pin according to their own conventions, provided that the functionality of the device is not altered from what is specified here.

19、Table 1 5-pin to 6-land pinout tableFunction(See Note)DescriptionPin Numbers1234561G00 Single 2-input NAND gate A B GND Y DNU VDD1G02 Single 2-input NOR gate A B GND Y DNU VDD1G04 Single inverter DNU A GND Y DNU VDD1GU04 Single unbuffered inverter DNU A GND Y DNU VDD1G05 Inverter with open-drain out

20、put DNU A GND Y DNU VDD1G06 Inverter with open-drain output DNU A GND Y DNU VDD1G07 Single buffer/driver with open-drain output DNU A GND Y DNU VDD1G08 Single 2-input AND gate A B GND Y DNU VDD1G14 Single inverter with Schmitt-trigger input DNU A GND Y DNU VDD1G17 Single buffer/driver with Schmitt-t

21、rigger input DNU A GND Y DNU VDD1G32 Single 2-input OR gate A B GND Y DNU VDD1G34 Single buffer DNU A GND Y DNU VDD1G38 Single 2-input NAND gate w/ open-drain output A B GND Y DNU VDD1G66 Single analog switch I/O I/O GND OE DNU VDD1G79 D-type flip-flop with Q output D CK GND Q DNU VDD1G80 D-type fli

22、p-flop with Q output D CK GND Q DNU VDD1G86 Single 2-input XOR gate A B GND Y DNU VDD1G125 Single buffer/driver with 3-state outputs OE A GND Y DNU VDD1G125 Single bus switch OE A GND B DNU VDD1G126 Single buffer/driver with 3-state outputs OE A GND Y DNU VDDJEDEC Standard No. 75-5Page 3NOTE 1 The f

23、unction designation refers to the part designation of a series of commercial logic parts common in the industry. This number is normally preceded by a series of manufacturer specific characters to make up a complete part designation.NOTE 2 DNU means Do Not Use. This designation requires that the pri

24、nted circuit landing-pad for this device terminal remain unconnected to any signal or supply potential. It must remain an open circuit. This device terminal might be connected to active or inactive circuitry within the device.3.4 Pin conversion from 6-pin DIP to 6-land SON packageThe pinout adopts t

25、he naming convention of logic devices in 6-pin DIP packages. The signal nomenclature used in this table is intended to define the functionality of each pin and not require that a specific naming convention be followed. Each product vendor is free to name the pin according to their own conventions, p

26、rovided that the functionality of the device is not altered from what is specified here.1G240 Single inverter with 3-state outputs OE A GND Y DNU VDD1G384 Single bus switch A B GND OE DNU VDDTable 2 6-pin to 6-land pinout tableFunction DescriptionPin Numbers1234562G04 Dual inverter 1A GND 2A 2Y VDD1

27、Y2GU04 Dual unbuffered inverter 1A GND 2A 2Y VDD1Y2G06 Dual inverter with open-drain outputs 1A GND 2A 2Y VDD1Y2G07 Dual buffer/driver with open-drain outputs 1A GND 2A 2Y VDD1Y1G10 Single 3-input NAND gate A GND B Y VDDC1G11 Single 3-input AND gate A GND B Y VDDC2G14 Dual inverter with Schmitt-trig

28、ger inputs 1A GND 2A 2Y VDD1Y2G16 Dual buffer 1A GND 2A 2Y VDD1Y2G17 Dual buffer/driver with Schmitt-trigger inputs 1A GND 2A 2Y VDD1Y1G18 1-of-2 non-inverting demux with 3-state output S GND A 1Y VDD0Y1G19 1-of-2 decoder/multiplexer A GND OE 1Y VDD0Y1G27 Single 3-input NOR A GND B Y VDDC2G34 Dual b

29、uffer/driver 1A GND 2A 2Y VDD1Y1G57 Universal configurable 2-input gate In1 GND In0 Y VDDIn21G58 Universal configurable 2-input gate In1 GND In0 Y VDDIn21G97 Universal configurable 2-input gate In1 GND In0 Y VDDIn21G98 Universal configurable 2-input gate In1 GND In0 Y VDDIn21G157 Single 2-input non-

30、inverting multiplexer In1 GND In0 Y VDDS1G158 Single 2-input inverting multiplexer In1 GND In0 Y VDDS1G175 Single D-type flip-flop CK GND D Q VDDCLR1G332 Single 3-input OR A GND B Y VDDCTable 1 5-pin to 6-land pinout tableFunction(See Note)DescriptionPin Numbers1234563 Pinout standard (contd)JEDEC S

31、tandard No. 75-5Page 4NOTE 1 The function designation refers to the part designation of a series of commercial logic parts common in the industry. This number is normally preceded by a series of manufacturer specific characters to make up a complete part designation.NOTE 2 DNU means Do Not Use. This

32、 designation requires that the printed circuit landing-pad for this device terminal remain unconnected to any signal or supply potential. It must remain an open circuit. This device terminal might be connected to active or inactive circuitry within the device.3.5 8-land QFN package (MO-255, variatio

33、n UAAD)Figure 2 Pinout configuration - Bottom view3.6 Pin conversion from 8-pin DIP to 8-land QFN packageThe pinout adopts the naming convention of logic devices in 8-pin DIP packages. The signal nomenclature used in this table is intended to define the functionality of each pin and not require that

34、 a specific naming convention be followed. Each product vendor is free to name the pin according to their own conventions, provided that the functionality of the device is not altered from what is specified here.1G386 Single 3-input XOR A GND B Y VDDC1G373 Single D-type latch LE GND D Q VDDOE1G374 S

35、ingle D-type flip-flop CK GND D Q VDDOE1G3157 SPDT analog switch I/O2 GND I/O1 COM VDDS1G3257 2-to-1 bus-switch multiplexer B2 GND B1 A VDDSTable 3 Generic conversion from 8-pin DIP package to 8-land QFN packagePackage Style Pin numbers8-pin DIP 123456788-land QFN 76543218Table 2 6-pin to 6-land pin

36、out tableFunction DescriptionPin Numbers1234563 Pinout standard (contd)JEDEC Standard No. 75-5Page 53 Pinout standard (contd)Table 4 8-pin to 8-land pinout tableFunc-tionDescriptionPin Numbers123456782G00 Dual 2-input NAND gate 1Y 2B 2A GND 2Y 1B 1A VDD2G02 Dual 2-input NOR gate 1Y 2B 2A GND 2Y 1B 1

37、A VDD2G08 Dual 2-input AND gate 1Y 2B 2A GND 2Y 1B 1A VDD2G32 Dual 2-input OR gate 1Y 2B 2A GND 2Y 1B 1A VDD2G38 Dual 2-input NAND gate with open-drain output1Y 2B 2A GND 2Y 1B 1A VDD2G53 Dual analog MUX/DEMUX I/O1 I/O2 S GND GND INH COM VDD2G66 Dual analog switch 1OE 2I/O 2I/O GND 2OE 1I/O 1I/O VDD

38、2G74 Single D-type flip-flop PRE CLR Q GND Q DCKVDD2G79 Dual D-type flip-flop 1Q 2D 2CK GND 2Q 1D 1CK VDD2G80 Dual D-type flip-flop with inverting Q outputs1Q 2D 2CK GND 2Q 1D 1CK VDD2G86 Dual 2-input XOR gate 1Y 2B 2A GND 2Y 1B 1A VDD2G125 Dual buffer/driver with 3-state outputs2OE 1Y 2A GND 2Y 1A

39、1OE VDD2G126 Dual buffer/driver with 3-state outputs2OE 1Y 2A GND 2Y 1A 1OE VDD2G132 Dual 2-input NAND gate with schmitt-trigger inputs1Y 2B 2A GND 2Y 1B 1A VDD2G139 Single 2-to-4 decoder Y1 Y2 Y3 GND Y4 B A VDD2G157 Single MUX/DEMUX G S Y GND Y BAVDD2G240 Dual inverting buffer with 3-state outputs2

40、OE 1Y 2A GND 2Y 1A 1OE VDD2G241 Dual buffer/driver with 3-state outputs2OE 1Y 2A GND 2Y 1A 1OE VDD2G244 Dual buffer/driver with 3-state outputs2OE 1Y 2A GND 2Y 1A 1OE VDD3G04 Triple inverter 1Y 3A 2Y GND 2A 3Y 1A VDD3GU04 Triple unbuffered inverter 1Y 3A 2Y GND 2A 3Y 1A VDD3G05 Triple inverter with

41、open-drain outputs1Y 3A 2Y GND 2A 3Y 1A VDD3G06 Triple inverter with open-drain outputs1Y 3A 2Y GND 2A 3Y 1A VDD3G07 Triple buffer/driver with open-drain outputs1Y 3A 2Y GND 2A 3Y 1A VDD3G14 Triple inverter with Schmitt-trigger inputs1Y 3A 2Y GND 2A 3Y 1A VDDJEDEC Standard No. 75-5Page 6NOTE The fun

42、ction designation refers to the part designation of a series of commercial logic parts common in the industry. This number is normally preceded by a series of manufacturer specific characters to make up a complete part designation.NOTE DNU means Do Not Use. This designation requires that the printed

43、 circuit landing-pad for this device terminal remain unconnected to any signal or supply potential. It must remain an open circuit. This device terminal might be connected to active or inactive circuitry within the device.4 Reference to other applicable JEDEC standards and publicationsJEP95, JEDEC R

44、egistered and Standard Outlines for Solid State and Related Product3G17 Triple buffer/driver with Schmitt-trigger inputs1Y 3A 2Y GND 2A 3Y 1A VDD3G34 Triple buffer/driver 1Y 3A 2Y GND 2A 3Y 1A VDDTable 4 8-pin to 8-land pinout tableFunc-tionDescriptionPin Numbers123456783 Pinout standard (contd)Rev.

45、 9/02Standard Improvement Form JEDEC JESD75-5 The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard. Individuals or companies are invited to submit comments to JEDEC. All comments will be collected and dispersed

46、to the appropriate committee(s).If you can provide input, please complete this form (can be edited with Acrobat Reader) and return to:JEDECAttn: Publications Department2500 Wilson Blvd. Suite 220Arlington, VA 22201-3834Fax: 703.907.75831. I recommend changes to the following: Requirement, paragraph number Test method number Paragraph number The referenced paragraph number has proven to be:Unclear Too Rigid In ErrorOther 2. Recommendations for correction:3. Other suggestions for document improvement:Submitted byName: Phone:Company: E-mail:Address: City/State/Zip: Date: