JEDEC JEP156A-2018 Chip-Package Interaction Understanding Identification and Evaluation.pdf

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1、 JEDEC PUBLICATION Chip-Package Interaction Understanding, Identification, and Evaluation JEP156A (Revision of JEP156, March 2009) MARCH 2018 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the J

2、EDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of p

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5、ons represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No cla

6、ims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standa

7、rds and Documents for alternative contact information. Published by JEDEC Solid State Technology Association 2018 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this

8、file the individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State

9、Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Publication No. 156A -i- CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION, AND EVALUATION Introduction The present solid state

10、 component level test structures or procedures do not always ensure that problems associated with chip-package interactions (CPI) are discovered in standard device level qualifications. As component structures integrate ultra low-k (ULK) chip level dielectrics to increase performance, the interactio

11、n between the device and the package increases, though these interactions can be found in prior technologies. This document discusses identification and evaluation methods to evaluate the effect of chip package interactions on product reliability. JEDEC Publication No. 156 -ii- JEDEC Publication No.

12、 156A Page 1 CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION GUIDELINE (From JEDEC Board Ballot JCB-18-12, formulated under the cognizance of the JC-14.3 Subcommittee on Silicon Devices Reliability Qualification and Monitoring.) 1 Scope This publication references a set of freq

13、uently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products. CPI test structures may not be a prerequisite for device qualification dependent on th

14、e device technology; however, if the effect of CPI on a device technology placed in a specific packaging scheme is not known, there could be reliability concerns for that component that are not evident with standard component level test structures. Therefore, it is recommended that CPI test structur

15、es are used and the associated testing and failure analysis be performed to determine if there are any adverse effects on that component due to packaging. Chip sizes and packages should be used that are representative of the product family to allow investigation of failure mechanisms for those produ

16、cts. NOTE This publication covers only interaction between the semiconductor package stresses and the semiconductor device. Interactions between the assembled component and a second level assembly are not covered. See JEP 150 for information regarding assembled component reliability. Interactions re

17、sulting from package interconnect electromigration are also not covered. See JEP 154 regarding Package interconnect electromigration. . See JEP158 for the effects on chip reliability due to through-silicon vias (TSVs). NOTE CPI tests should be performed in addition to process and package qualificati

18、on typically performed on new products. These reliability stress tests have been found capable of stimulating and precipitating failures in components in an accelerated manner, but these tests should not be used indiscriminately. Each qualification should be examined for: a) Any potential new and un

19、ique failure mechanism b) Any situations where these tests/conditions may induce invalid or overstress failures. In either case the set of reliability requirements, tests and/or conditions should be appropriately modified to properly include the new failure mechanisms and modes. This document does n

20、ot relieve the supplier of the responsibility to meet internal or customer specified qualification programs. JEDEC Publication No. 156A Page 2 2 Terms and definitions assembled state (of a component): The state of a component that has been attached to a second-level assembly. back-end-of-line (BEOL)

21、(adj): Pertaining to the portion of the semiconductor processing line that creates the conductive lines carrying power and signals between devices and to the interface connecting off-chip. back end of line (BEOL)(noun): The portion of the semiconductor processing line that creates the conductive lin

22、es carrying power and signals between devices and to the interface connecting off-chip. bond and assembly processes (B level 1 (L1) interconnect: The structure that connects the chip to the substrate. NOTE 1 For the purpose of this document chip-to-substrate-interconnect will be referred to as “inte

23、rconnect”. NOTE 2 Examples of this structure include, but are not limited to, solder bumps or copper columns. NOTE 3 Level 1 (L1) interconnect is not associated with JP 001 Foundry Level 1 Qualification (L1). failure mechanism: The physical, chemical, electrical, or other process that has led to a n

24、onconformance. NOTE 1 See JESD671, Component Quality Problem Analysis and Corrective Action Requirements. NOTE 2 A failure mechanism may be characterized by how a degradation process proceeds including the driving force, e.g., oxidation, diffusion, electric field, current density. failure mode (gene

25、ral): The way in which a failure mechanism manifests itself in a failing component. NOTE Examples of failure modes are a visual blemish, a bent lead, a foreign particle or material, an incorrect dopant profile or grain size, a scratch, an electrical fault (open, short, leakage, inadequate slew rate

26、or noise margin, stuck at high or low, etc.). far-back-end-of-line (FBEOL)(adj): Pertaining to the portion of the semiconductor processing line that creates the metal layers (including the under-bump metal UBM or redistribution layer) and associated interconnect structures forming the connection bet

27、ween the chip and the outside world by conductors, e.g., bond wires, bumps, balls, via. JEDEC Publication No. 156A Page 3 2 Terms and definitions (contd) far back end of line (FBEOL)(noun): The portion of the semiconductor processing line that creates the metal layers (including the under-bump metal

28、 UBM or redistribution layer) and associated interconnect structures forming the connection between the chip and the outside world by conductors, e.g., bond wires, bumps, balls, via. free-standing state (of a component): The state of a component that is not attached to the next level of assembly pac

29、kaging. front-end-of-line (FEOL)(adj): Pertaining to the portion of the semiconductor processing line that creates active devices, ending with the gate oxide conductors. front end of line (FEOL)(noun): The portion of the semiconductor processing line that creates active devices, ending with the gate

30、 oxide conductors. packaged device: A semiconductor device within an enclosure that allows electrical connection to, and provides mechanical and environmental protection for, that device. second-level assembly: The attachment of a component to the next level of assembly packaging. substrate (of a se

31、miconductor device) (general): The supporting material upon which or within which the elements of a semiconductor device are fabricated or attached. under-bump metal (UBM): The metal layers located between the solder bump or column and the die. 3 Reference documents JEP122, “Failure Mechanisms and M

32、odels for Silicon Semiconductor Devices” JEP131, “Process Failure Modes and Effect Analysis (FMEA)” JEP150, “Stress-test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Components” JEP154, “Guideline for Characterizing Solder Bump Electromigration u

33、nder Constant Current and Temperature Stress” JESD22, “Reliability Test Methods for Packaged Devices” JESD47, “Stress-Test-Driven Qualification of Integrated Circuits” JESD74, “Early Life Failure Rate Calculation Procedure for Electronic Components” JESD85, “Methods for Calculating Failure Rate in U

34、nits of FITs” JESD91, “Method for Developing Acceleration Models for Electronic Component Failure Mechanisms” JESD94, “Application Specific Qualification using Knowledge Based Test Methodology” JP001, “Foundry Process Qualification Guidelines” JEP158, “3d Chip Stack with Through-Silicon Vias (TSVS):

35、 Identifying, Evaluating and Understanding Reliability Interactions” JEDEC Publication No. 156A Page 4 4 Understanding CPI CPI stresses arise from the processes and materials used in attaching and encapsulating a chip forming a functional module. Thermal excursions, either alone, or in combination w

36、ith mismatches in material properties, such as coefficient of thermal expansion (CTE), are a major source of mechanical stress on the chip. With increasing chip size, CTE mismatch and associated stress increase, that can result in CPI concerns. Processing defects, such as dicing cracks or chip backs

37、ide flaws, can serve as initiation points for CPI failure. Material defects such as particles in a thermal conduction adhesive can serve as stress concentrators to promote CPI fails. Material interactions such as alloy or intermetallic formation can cause volume changes which concentrate stress. Low

38、-k dielectric materials in the chip are mechanically weak and tend to form weak interfaces with other materials. An improper cooling rate during chip attach to substrate can cause CPI failures. And solder bump solidification, particularly on lead-free flip chip modules, if not uniform, can also conc

39、entrate CTE stress. Bond and assembly processes include solder bump attach, wafer dice, chip reflow, underfill and cure, thermal enhancement apply, encapsulation, module test, burn-in, module card attach, and rework of any of these processes for flip chip plastic ball grid arrays (FCPBGA) and simila

40、r module types. The critical materials are the substrate, interconnect, underfill, and thermal enhancement on the back of the chip, heat spreader, heatsink, if any, and card. Wire bond processes include wafer dice, chip attach, wire bond, mold compound dispense and cure, card attach, and reworks. Th

41、e critical materials are the package, wire, mold, and card. It is worth examining a few examples of potential CPI failures to highlight the critical contributors to the failures: Underfill can crack during simulated or actual on/off cycles, either in stress testing or in the field. The CTE mismatch

42、between chip and package concentrates strain at the corner of the chip during the cold portion of the thermal cycle, causing a crack which propagates out from the corner. As the crack propagates, it opens up either the chip-underfill interface, or at another weak interface, causing either interconne

43、ct fatigue, or an electrical fail in the chip dielectric. Particles in a material used to provide a good cooling path between the top of the chip and the cap can initiate a crack that, during on/off cycles, can propagate through the chip to the active devices and chip wiring. Care is needed to ensur

44、e that the maximum particle size does not exceed the intended chip-to cap-gap. Flip chip solder ball interconnects solidify after chip join reflow as individuals. If fast cool down causes, for example, outer balls to solidify first, the strain from CTE mismatch is concentrated at their contact pads,

45、 and can cause cracking of the dielectric, providing a crack which can propagate, and also serve as an opening for humidity and corrosive contaminants to enter the chip. Saw dicing or laser grooving can introduce flaws in BEOL structures. These flaws can develop into cracks during reliability stress

46、ing (especially in thermal cycle stresses) and further grow and propagate to the crackstop along weak interfaces in the BEOL structures. The crackstop can then be breached by the cracks which gained energy in propagation particularly at chip corners. These cracks can then fail the chip once they rea

47、ch the active chip area within crackstop. Such cracks can also set up moisture degradation mechanisms (like TDDB). Without special protection, the cracks may also dive into the silicon and fail the FEOL devices. In those cases, FEOL monitoring is also recommended. JEDEC Publication No. 156A Page 5 4

48、 Understanding CPI (contd) These mechanisms may not show up in standard device stress testing due to the insensitivity of common test structures, even though the stress levels in the test may be much higher than those that can cause CPI fails. Mechanical stresses, which can scale with size, and defe

49、cts introduced by the far back end of the wafer line and bond and assembly processes, can only be addressed through representative test structure design and processing, followed by stress testing and appropriate electrical, physical and physio-chemical characterization, see 5. Through-silicon vias (TSVs) are used to enable 3D chip stacking. A chip containing TSVs is subject to experiencing a variety of reliability effects on BEOL and FEOL structures. For more detail on this area, refer to JEP158. 5 CPI failure concerns and associated hardware design considerations 5.1 Primary CPI re