JEDEC JEP156-2009 Chip-Package Interaction Understanding Identification and Evaluation.pdf

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1、JEDEC PUBLICATION Chip-Package Interaction Understanding, Identification and Evaluation JEP156 MARCH 2009 (Reaffirmed: JUNE 2012) JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board o

2、f Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and

3、 assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption

4、 may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represen

5、ts a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in

6、 conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Docu

7、ments for alternative contact information. Published by JEDEC Solid State Technology Association 2012 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the ind

8、ividual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology A

9、ssociation 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Publication No. 156 -i- Chip-Package Interaction Understanding, Identification and Evaluation Introduction The present solid state component lev

10、el test structures or procedures do not always ensure that problems associated with chip-package interactions (CPI) are discovered in standard device level qualifications. As component structures integrate ultra low-k (ULK) chip level dielectrics to increase performance, the interaction between the

11、device and the package increases, though these interactions can be found in prior technologies. This document discusses identification and evaluation methods to evaluate the effect of chip package interactions on product reliability. JEDEC Publication No. 156 -ii- JEDEC Publication No. 156 Page 1 Ch

12、ip-Package Interaction Understanding, Identification and Evaluation Guideline (From JEDEC Board Ballot JCB-09-13, formulated under the cognizance of the JC-14.3 Subcommittee on Silicon Devices Reliability Qualification and Monitoring.) 1 Scope This publication references a set of frequently recommen

13、ded and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products. CPI test structures may not be a prerequisite for device qualification dependent on the device techno

14、logy; however, if the effect of CPI on a device technology placed in a specific packaging scheme is not known, there could be reliability concerns for that component that are not evident with standard component level test structures. Therefore, it is recommended that CPI test structures are used and

15、 the associated testing and failure analysis be performed to determine if there are any adverse effects on that component due to packaging. Chip sizes and packages should be used that are representative of the product family to allow investigation of failure mechanisms for those products. NOTE This

16、publication covers only interaction between the semiconductor package stresses and the semiconductor device. Interactions between the assembled component and a second level assembly are not covered. See JEP 150 for information regarding assembled component reliability. Interactions resulting from pa

17、ckage interconnect electromigration are also not covered. See JEP 154 regarding Package interconnect electromigration. NOTE CPI tests should be performed in addition to process and package qualification typically performed on new products. These reliability stress tests have been found capable of st

18、imulating and precipitating failures in components in an accelerated manner, but these tests should not be used indiscriminately. Each qualification should be examined for: a) Any potential new and unique failure mechanism b) Any situations where these tests/conditions may induce invalid or overstre

19、ss failures. In either case the set of reliability requirements, tests and/or conditions should be appropriately modified to properly include the new failure mechanisms and modes. This document does not relieve the supplier of the responsibility to meet internal or customer specified qualification p

20、rograms. JEDEC Publication No. 156 Page 2 2 Terms and definitions assembled state (of a component): The state of a component that has been attached to a second-level assembly. back-end-of-line (BEOL)(adj): Pertaining to the portion of the semiconductor processing line that creates the conductive lin

21、es carrying power and signals between devices and to the interface connecting off-chip. back end of line (BEOL)(noun): The portion of the semiconductor processing line that creates the conductive lines carrying power and signals between devices and to the interface connecting off-chip. bond and asse

22、mbly processes (B e.g. organic laminate or ceramic high TCE substrate. Once CPI reliability testing is done for the worst-case configuration, it may be possible that the CPI testing coverage for lower risk options has been covered. This, however, needs to be reviewed for the specific case. A CPI tes

23、t vehicle must be devised to evaluate the CPI integrity for any new chip to package type built with any new process or material in the BEOL, FBEOL, wafer backside grinding and polishing, wafer dicing or B&A sectors. A set of primary CPI reliability fail mechanism types are described below, followed

24、by test vehicle design considerations. JEDEC Publication No. 156 Page 7 5.1 Primary CPI reliability fail types requiring test vehicle evaluation (contd) 5.1.1 Chip-side BEOL and chip edge integrity failure Structural interruption of the BEOL wiring can occur due to thermal treatment of chip to packa

25、ge and appears as either interfacial delamination (adhesive failure) or physical film cracking (cohesive failure). Examples of the specific mechanisms which may lead to failure include, but are not limited to: 1. Weakening or loss of dielectric film adhesion 2. Reduction of dielectric mechanical str

26、ength 3. Dielectric breakage beneath the interconnection (e.g., solder bump structure 4. Dicing process crack propagation (Chip edge seal & crack stop integrity) 5. High DNP location cracking 6. Stress migration 7. Bump non-wet in flip chip 8. Metal peel-off in wire bond applications 9. Wire bond di

27、splacement 10. Passivation cracks Annex A lists the failure mechanisms and some reasons for their occurrence. 5.1.2 Chip to package interconnection integrity failure Failure of the UBM to the interconnect structure itself can be seen in a packaged device. Examples of these specific mechanisms includ

28、e, but are not limited to: 1. Interconnect fatigue during thermal cycling 2. Interconnect process defects, e.g., excessive UBM undercut 3. Process residues from plating or UBM fabrication 4. Interconnect nonplanarity resulting in marginal contact, especially at high DNP locations 5. Too fast a cooli

29、ng rate during chip attach to the substrate can cause bump cracking or UBM peeling. 5.2 Test vehicle design considerations If feasible, use of a test vehicle is suggested since actual product may not have the electrical test sensitivity to adequately isolate or detect CPI concerns or failures. Valid

30、ation of results on actual product is also recommended. Failure analysis of a test vehicle can be easier, if properly designed. JEDEC Publication No. 156 Page 8 5.2 Test vehicle design considerations (contd) 5.2.1 CPI chip, substrate and interconnect The CPI test chip and substrate should be careful

31、ly designed so as to provide adequate representation of worst-case structural and process integration attributes relating to BEOL chip side wiring, chip-to-package interconnect structure and laminate configuration. These structures should be included in the final reliability stress activity. 5.2.1.1

32、 CPI die The chip size should be maximized for reliability coverage that is representative of a product family, preferably to the worst case design. It is acceptable for the CPI test chip to be comprised primarily of BEOL levels. Inclusion of ESD protection structures is suggested for ease of parts

33、handling and elimination of non-CPI test failure modes. If ESD structures are not included, care must be taken in handling, stressing and testing operations. ESD protection structures provide the ultimate protection of the finished module from electrostatic charges that can create electrical fails i

34、ndependently of a CPI reliability mechanism. The BEOL film stack does not need to include every possible discrete build level available in a subject technology, but should be designed such that every possible BEOL interface is represented, and so as to capture a worst-case configuration of advanced

35、low-k dielectric layers. The specific materials and processes used to create the wafer level wiring structure (BEOL processes) and the individual finished die (wafer finishing processes) all should be included in the simulation build. This includes, but not limited to, special features such as crack

36、 stop or seal ring if they are present in the product or technology being tested. 5.2.1.2 CPI substrate The packaged device substrate is matched to the test vehicle chip size and representative of the product or technology being tested. The CPI substrate should be designed with a stress profile that

37、 is consistent with worst-case for the technology requiring reliability coverage. Particular consideration should be afforded to laminate core thickness, number of wiring levels, laminate materials, chip to die interconnections, copper loading, and overall laminate size. 5.2.1.3 Die to substrate int

38、erconnect The interconnection structure for the CPI Reliability exercise should be an interconnect type chosen as representative of the qualifying technology, and a worst-case with respect to transfer of stresses between the chip and the packaging substrate. This applies particularly to the solder a

39、lloy material, solder bump pitch, and solder bump process. The solder bump layout should be uniform and should include inactive solder bumps if necessary in order to create a product representative array configuration. Other types of interconnects include, but not limited to, die attach and down bon

40、ds. Use of modeling analysis may also be used to gain a better understanding of product interconnect configurations. The specific materials and processes used to create the UBM and interconnect bump structure should all be included in the simulation build. JEDEC Publication No. 156 Page 9 5.3 CPI ch

41、ip-level test structures Individual CPI test structures should be placed at multiple locations across the chip, with particular emphasis at high DNP locations, especially in the corner or close to the crack stop or seal ring, so that worst case stress effects are adequately covered by the reliabilit

42、y stress. A listing of potential failure modes and some examples of basic CPI structure types and stress tests that can be used to discover the specific failure modes in the application is given by Table 1. Other structures are possible based on experience and product design. The number of test stru

43、ctures used on a test die may be limited based on test capability and substrate wiring limitations. 5.3.1 Examples of CPI test structure type 5.3.1.1 Corner sensor (within die) Relatively short length continuity or chain structure that includes BEOL via to metal connections at all levels in the BEOL

44、 build stack, are wired out through level 1 interconnect (bumps, wire bonds, copper pillars, etc.) at either end. Structures are generally built to minimum line and space (pitch) rules for each metal layer. 5.3.1.2 Perimeter lines (within die) Single line or parallel line pair are placed as close to

45、 chip perimeter as possible, extending around the entire periphery of the chip at each metal layer. They are wired out through a single interconnect at each end (or an interconnect pair if a double line is used). The double line allows for detection of shorts, as well as, opens. If possible, it is r

46、ecommended that there be one perimeter line structure at each BEOL metal layer. If using perimeter line(s), it is recommended that there be intermediate test points to help isolate failure locations. 5.3.1.3 Interconnect stitch chains (die to substrate) Daisy-chain vertically wired repeating interco

47、nnect to via structures are connected by wire lengths at one or more of the BEOL wiring layers. Several individually wired test chain structures should be placed on the chip at multiple distance to neutral point (DNP) locations, including chip center and along chip edges. 5.3.1.4 BEOL serpentines (w

48、ithin die) Within BEOL level metal wiring with interleaved comb and serpentine structures, built at minimum ground rule pitch may be included. Several individually wired structures may be placed on chip in multiple locations. JEDEC Publication No. 156 Page 10 5.3.1 Examples of CPI test structure typ

49、e (contd) 5.3.1.5 BEOL via chains (within die) Vertically wired, repeating via chain lengths, wired between two or more BEOL wiring levels that use tight line and space pitch, consistent with product being tested, should also be included. Several individually wired structures may be placed on the chip at multiple DNP locations, including chip center and along chip edges. The primary design objective is to detect BEOL cracking with CPI test structures arranged so that the test chip appears similar to a typical product chip with respect to critical layout parameters and interconnec