JEDEC JEP155A 01-2012 Recommended ESD Target Levels for HBM MM Qualification (Editorial Revision of JEP155A January 2012).pdf

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1、JEDEC PUBLICATION Recommended ESD Target Levels for HBM/MM Qualification JEP155A.01 (Editorial Revision of JEP155A, January 2012) MARCH 2012 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JE

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10、EDEC Publication No. 155A.01 -i- RECOMMENDED ESD TARGET LEVELS FOR HBM/MM QUALIFICATION Contents Foreword ii Introduction ii 1 Scope1 2 References1 3 Terms, definitions, and letter symbols .4 4 Historical Perspective on HBM/MM ESD Requirements 5 4.1 Motivation for the HBM Target Level .5 4.2 Motivat

11、ion for Introducing Machine Model (MM) 5 5 Changes and Improvements in ESD and Control Environment .6 5.1 Historic ESD Handling Procedures6 5.2 Global Implementation of ESD Control.7 5.2.1 Ground and Bond all Conductors:8 5.2.2 Control Charges on Insulators8 5.2.3 Use Protective Packaging for Transi

12、t and Storage .8 5.2.4 ESD Control Programs and Resulting Data .8 5.2.5 Advantage of Process Analysis 10 5.3 Change of HBM Hazard Scenario by Increasing the Automation Level12 6 Machine Model Correlation between HBM and MM ESD.12 6.1 HBM vs. MM.12 6.1.1 Consequence of 1 kV HBM Target14 6.2 Exception

13、s to HBM/MM Ratio 15 6.2.1 Bipolar vs. Unipolar Stress.15 6.2.2 Advanced Technologies .16 6.3 Conclusions18 7 Consolidated Industry Data on HBM Levels vs. Field Returns18 7.1 Field Return Rates versus HBM Level.18 7.2 Case Studies .21 7.2.1 Devices with Failure Levels below 500 V HBM21 7.2.2 Devices

14、 that Fail between 500-1000 V HBM 21 7.2.3 Devices that Fail between 1000-2000 V HBM.22 7.3 Conclusion .22 8 Impact of ESD Requirements from Customers and Suppliers23 8.1 ESD Requirements and Specification Failures.23 8.2 Impact of “ESD Failures”.23 8.3 Impact of Revised ESD Target Levels .25 9 IC T

15、echnology Scaling Effects on Component Level ESD26 9.1 Scaling Effects on ESD Robustness .26 9.2 Protection Design Window 29 9.3 ESD Capacitive Loading Requirements.31 9.4 Package Effects 34 9.5 ESD Technology Roadmap35 10 Differences between Component ESD and System Level ESD .36 10.1 The History o

16、f System Level ESD .36 10.2 Differences in Component and System Level ESD Stress Models 36 10.3 Case Studies .38 10.4 Conclusion .38 11 Recommendations for New ESD Target Levels.39 11.1 New Realistic Target Levels for HBM and MM39 11.2 Treatment of Special Pins.40 11.3 Timeframe for Applying New Rec

17、ommendations .40 11.4 Future Cost of ESD Design40 11.5 Product ESD Evaluation Criteria41 11.6 Looking Forward42 Annex A (informative) Frequently Asked Questions43 Annex B (informative) Differences between JEP155A.01 and JEP155A .49 JEDEC Publication No. 155A.01 -ii- RECOMMENDED ESD TARGET LEVELS FOR

18、 HBM/MM QUALIFICATION Foreword For more than 20 years, IC component level ESD target levels for both HBM (2 kV) and MM (200 V) have essentially stayed constant, with no focus on data to change these levels. Todays enhanced static control methods required by OEMs do not justify these higher HBM/MM le

19、vels as data will show in this document. ESD over-design to these levels in todays latest silicon technologies is increasingly constraining silicon area as well as performance, and is leading to more frequent delays in the product innovation cycle. Based on improved static control technology, field

20、failure rate, case study and ESD design data, collected from IC suppliers and contract manufacturers, we propose more realistic and safe HBM/MM ESD target levels. These new levels (1 kV HBM / 30 V MM) are easily achievable with static control methods mandated by customers and with todays modern ESD

21、design methods. Introduction This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD level requirements. It will be shown through this document why realistic modifying of t

22、he ESD target levels for component level ESD is not only essential but is also urgent. The document is organized in different sections to give as many technical details as possible to support the purpose given in the abstract. Additionally, Frequently Asked Questions (FAQ) in the annex are intended

23、to avoid any misconceptions that commonly occur while interpreting the data and the conclusions herein. All component level ESD testing specified within this document adheres to the methods defined in the appropriate JEDEC and ESDA/ANSI specifications. In June 2009, the formulating committee unanimo

24、usly approved the addition of the ESDA logo on the covers of this document. JEDEC Publication No. 155A.01 Page 1 RECOMMENDED ESD TARGET LEVELS FOR HBM/MM QUALIFICATION (From JEDEC Board Ballot JCB-08-41, and JCB-11-82, formulated under the cognizance of the JC-14 Committee on Quality and Reliability

25、 of Solid State Products.) 1 Scope The intent of this report is to document and provide critical information to assess and make decisions on safe ESD level requirements. The scope of this document is to provide this information to quality organizations in both semiconductor companies and their IC cu

26、stomers. 1.1 Special Notes on the System Level ESD 1. This work and the recommendations therein are intended for Component Level safe ESD requirements and will have little or no effect on system level ESD results. 2. Systems and System boards should continue to be designed to meet appropriate ESD th

27、reats regardless of the components in the systems that are meeting the new recommendations from this work, and that all proper system reliability must be assessed through the IEC test method. 1.2 Special Notes on the Machine Model 1. The Machine Model (MM) method as specified by some customers and s

28、uppliers is not a preferred methodology by JEDEC for use in place of or in addition to HBM and CDM test protocols. 2. In contrast to HBM testers, MM testers are known to have wide variations in output results and thus can give relatively less accurate information from user to user. 2 References 1. W

29、.M. King, “Dynamic waveform Characteristics of Personnel Electrostatic Discharge”, EOS/ESD Symposium Proceedings, EOS-1, 78 (1979). 2. L. Avery, private communication. 3. D.L. Lin, M.S. Strauss, and T.L. Welsher, “On the Validity of ESD Threshold Data Obtained Using Commercial Human-Body Model Simul

30、ators”, Proceedings of the 25th International Reliability Physics Symposium, 77 (1987). 4. M.S. Strauss, D.L. Lin, and T.L. Welsher, “Variations in Failure Modes and Cumulative Effects Produced by Commercial Human-Body Model Simulators”, EOS/ESD Symposium Proceedings, EOS-9, 59-63 (1987). 5. ANSI/ES

31、D S20.20-1999; Protection of Electrical and Electronic Parts, Assemblies and Equipment (Excluding Electrically Initiated Explosive Devices) 6. IEC 61340-5-1; Electrostatics Part 5: Specification for the protection of electronic devices from electrostatic phenomena Section 1: General requirements; 12

32、.1998 JEDEC Publication No. 155A.01 Page 2 2 References (contd) 7. R. Gaertner; Do we expect ESD-failures in an EPA designed according to international standards? The need for a process related risk analysis; ESD Symposium 2007; Anaheim, CA, USA 8. ANSI/ESD STM5.1-2001 or JESD22-A114C.01 9. ANSI/ESD

33、 STM5.2-1999 or JESD22-A115-A 10. M. Kelly et al., A Comparison of Electrostatic Discharge Models and Failure Signatures for CMOS Integrated Circuit Devices, EOS/ESD Symposium, pp. 175-185, 1995 11. A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, 2002 12. G. Notermans et al., Pitf

34、alls When Correlating TLP, HBM and MM Testing, EOS/ESD Symposium, pp. 170-176, 1998 13. M.D. Ker et al., Electrostatic discharge implantation to improve machine-model ESD robustness of stacked NMOS in mixed I/O interface circuits, ISQED, pp. 363-368, 2003 14. D. Pierce, ESD Failure Mechanisms, ESD S

35、ymposium Tutorial, 1995-2005 15. J. Whitfield et al., ESD MM Failures resulting from transient reverse currents, 44th IEEE IRPS, pp. 136-139, 2006 16. C. Duvvury and G. Boselli, “ESD and latch-up reliability for nanometer CMOS technologies,” IEDM, pp. 933-936, 2004. 17. S. Voldman, “ESD robustness a

36、nd scaling implications for Aluminum and Copper interconnects in advanced semiconductor technology,” ESD Symp. 1997. 18. K.H. Oh, K. Banerjee, C. Dvvury and R. Dutton, “Non-uniform conduction induced reverse channel length dependence of ESD reliability for silicided NMOS transistors,” IEDM, pp. 341-

37、344, 2002. 19. G. Boselli, J. Rodriguez, C. Duvvury, V. Reddy, P.R. Chidambaram and B. Hornung, “Technology scaling effects on the ESD design parameters in sub-100nm CMOS transistors,” IEDM, pp. 507-510, 2003. 20. C. Russ, H. Gossner, T. Schultz, N. Chaudhary, K. Schruefer, W. Xiong, A. Marhsall, C.

38、 Duvvury and C. Cleavelin, “ESD Evaluation of the emerging MuGFET technology, EOS/ESD Symp. 2005. 21. H. Gossner, C. Russ, F. Siegelin, J. Schneider, K. Schruefer, T. Schlutz, C. Duvvury, R. Cleavelin and W. Xiong, “Unique ESD failure mechanisms in a MuGFET technology,” IEDM 2006. 22. A. Salman, R G

39、authier, E. Wu, P. Riess, C. Putnam, M. Muhammad, J. Woo, D. Ioannou, “Electrostatic Discharge induced oxide breakdown characterization in a 0.1 um CMOS technology,” IRPS 2002. 23. A. Ille, W. Stadler, A. Kerber, T. Pompi, T. Brodbeck, K. Esmark and A. Bravix, “Ultra-thin gate oxide reliability in t

40、he ESD time domain,” EOS/ESD Symp. pp. 285-294, 2006. 24. G. Boselli, J. Rodriguez, C. Duvvury and J. Smith, “Analysis of ESD protection components in 65nm CMOS technology: scaling perspective and impact on ESD design window,” EOS/ESD Symp. 2005. 25. A. Jahanzeb, Y. Lin, S. Marum, J. Scichl, and C.

41、Duvvury, “Investigation of device body size on CDM tester peak currents and variability,” International ESD Workshop, 2007. 26. M. Mergens et al., “Diode- Triggered SCR (DTSCR) for RF-ESD Protection of BiCMOS SiGe and CMOS Ultra-Thin Gate Oxides”, IEDM Digest, 2003. 27. ESD Association Road Map: htt

42、p:/www.esda.org/ JEDEC Publication No. 155A.01 Page 3 2 References (contd) 28. ESD Association White Paper II: Trends in Silicon Technology and ESD Testing, 2006. 29. IEC standard 61000-4-2 edition 1.2, 2001 “EMC Part 4.2: Testing and Measurement Techniques ESD Immunity Test” 30. W. Stadler “State-o

43、f-the-Art in ESD Standards”, Proc. of 1stInternational ESD Workshop, Lake Tahoe, 2007, pp. 127-147, 2007 31. W. Stadler, S. Bargstaedt-Franke, T. Brodbeck, R. Grtner, M. Goroll, H. Gossner, N. Jensen and C. Mller “From the ESD Robustness of Products to the System ESD Robustness”, EOSESD Symp., 2004,

44、 pp. 67, 2004 32. S. Marum, R. Watson, and C. Duvvury, “Effects of Low Level IEC 61000-4-2 Stress on Integrated Circuits” Proc. of 1stInternational ESD Workshop, Lake Tahoe, 2007, pp. 262-273, 2007 33. W. Stadler, T. Brodbeck, R. Grtner and H. Gossner “Cable Discharges into Communication Interfaces”

45、, EOSESD Symp., 2006, pp. 144-151, 2006. 34. B. Reynolds, M. Muhammad and R. Gauthier , “A Test Method to Determine Cable Discharge Event Sensitivity at the Module Level”, Proc. of 1stInternational ESD Workshop, Lake Tahoe, 2007, pp. 252-261, 2007 35. T. Smedes, J. Van Zwol, G. De Raad, T. Brodbeck

46、and H. Wolf, “Relations Between System Level ESD and (vf-) TLP”, EOSESD Symp., 2006, pp. 136-143, 2006 36. N. Lacrampe, F. Caignet, M. Bafleur and N. Nolhier, “VF-TLP based methodology for the prediction of ESD immunity of a PCB”, Proc. of 1stInternational ESD Workshop, Lake Tahoe, 2007, pp. 240-251

47、, 2007. 37. S. Marum, D. Wang and A. Chadwick “Monitoring Clamp Voltage during IEC 61000-4-2 Stress”, Proc. of 1stInternational ESD Workshop, Lake Tahoe, 2007, pp. 450-457, 2007 38. J. Barth, J. Richner and L. G. Henry “System Level ESD Radiation Test Far Exceeds Real Human Metal Discharge”, Proc. o

48、f 1stInternational ESD Workshop, Lake Tahoe, 2007, pp. 467-478, 2007 39. J_H Ko, S_J Kim, K_S Im, K-K Jeon, S-J Song, C-S Kim, C-H Jeon, K-T Lee, H-G Kim, I-H Son “Abnormal HBM and MM Stress at Mobile LCD Module by Set-ESD gun”, Proc. of 1stInternational ESD Workshop, Lake Tahoe, 2007, pp. 450-457,

49、2007 40. White Paper II: Trends in Semiconductor Technology and ESD Testing, ESD Association, http:/www.esda.org 41. EIAJ ED4701; Environmental and endurance test methods for semiconductor devices 42. JESD22-A114; Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) 43. JESD22-A115; Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) JEDEC Publication No. 155A.01 Page 4 3 Terms, definitions, and letter symbols BGA ball grid array CDE cable discharge event CDM charged-device model CM contract manufacturer DIP dual-in-lin