JEDEC JEP149-2004 Application Thermal Derating Methodologies《热减额法应用》.pdf

《JEDEC JEP149-2004 Application Thermal Derating Methodologies《热减额法应用》.pdf》由会员分享，可在线阅读，更多相关《JEDEC JEP149-2004 Application Thermal Derating Methodologies《热减额法应用》.pdf（18页珍藏版）》请在麦多课文档分享上搜索。

1、JEDEC PUBLICATION Application Thermal Derating Methodologies JEP149 NOVEMBER 2004 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and

2、approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtain

3、ing with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or

4、processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and

5、 application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication shoul

6、d be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Published by JEDEC Solid State Technology Association 2004 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By dow

7、nloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE

8、 LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Ar

9、lington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Publication No. 149 -i- APPLICATION THERMAL DERATING METHODOLOGIES Introduction Derating refers to the method of setting a value within the manufacturers specifications for environmental or operational maximum use conditions. This practice ha

10、s been used to provide greater functionality margin within the manufacturers specifications, and, with the assistance of the manufacturer, potentially extend useful life or increase reliability. The process presented here is not a casual analysis, but is intended to be a part of a more sophisticated

11、 application analysis process performed by highly informed engineering staff working closely with the respective experts from the component manufacturer(s). Derating can be used as a mitigation response to various uncertainties surrounding: the specification limit given by the component manufacturer

12、, the actual use environmental conditions, the approximate nature of mathematical models normally employed. Traditionally, users of electronic components have employed various methods for derating. They include assigning a maximum percentage of the manufacturer specification limit, setting absolute

13、limits, or absolute margin value from the manufacturer specification limit. While design margin is desirable, stacking of multiple sources of margin can result in high costs, lost opportunities and, potentially, increased failures (i.e. some failure mechanisms are inversely dependent on temperature)

14、. Sources of margin include: conservative estimates of the operational characteristics of the application, component manufacturer specification limit margin, application derating methods. The practice of derating requires a good understanding of the manufacturers absolute maximum ratings, specificat

15、ion limits, and the consequences of approaching them. These ratings should have their foundation in the physical failure mechanisms and performance limitations associated with the component or technology in question. Also needed is a good understanding of the application use conditions and how the a

16、ppropriate stress conditions can be derived from them for comparison to the manufacturers specification limits. This illustrates the need for close communication with the component manufacturer. Manufacturers specification limits are typically derived from a combination of technology capability, des

17、ign, margin and marketing objectives. It should be noted that many of these limits are interrelated with other specifications, such as the junction temperature relationship with ambient air or case temperature through the thermal resistance of the various mechanical interfaces between them. Where su

18、ch interrelationships exist, prudent derating of selected operational, performance or environmental conditions may make it possible to extend other specification limits such that the application required performance and reliability meet requirements. In these cases, the parameter or physical element

19、 most closely connected with the associated failure mechanism or required functional performance takes precedence. For example, if electromigration is a concern and it is affected by junction temperature, then junction temperature should be managed. Adjustments can occur with other related elements

20、so long as the junction temperature is within the desired limits. These elements may include ambient air temperature or thermal resistance through thermal planes or heat sinks, power dissipation through clock speed, operational voltage, output drive (fan-out) or others. JEDEC Publication No. 149 -ii

21、- JEDEC Publication No. 149 Page 1 APPLICATION THERMAL DERATING METHODOLOGIES (From JEDEC Board Ballot JCB-04-93, formulated under the cognizance of the JC-14.3 Subcommittee on Silicon Devices Reliability Qualification and Monitoring.) 1 Scope This publication applies to the application of integrate

22、d circuits and their associated packages in end use designs. It summarizes the methodology of thermal derating and the suitability of such methodologies. NOTE This publication advocates the use of derating, but leaves the amount of derating up to the user. This should vary depending on many applicat

23、ion requirements including reliability, criticality, functional performance needs, etc. Also note that mechanical related mechanisms (such as vibration, shock, etc.) may not be suitable for derating per the methodology described here. 2 References JEP122 Failure Mechanisms and Models for Semiconduct

24、or Devices JEP143 Solid State Reliability Assessment and Qualification Methodologies JESD47 Stress Test Driven Qualification of Integrated Circuits JESD51 Methodology for the Thermal Measurement of Component Packages JESD69 Information Requirements for the Qualification of Silicon Devices JESD85 Met

25、hods for Calculating Failure Rates in Units of FITs JESD94 Application Specific Qualification Using Knowledge Based Test Methodology 3 Terms and definitions For the purposes of this standard, the following definitions apply. Derating: The practice of using an electronic device in a narrower environm

26、ental and/or operating envelope than its manufacturer designated limits. Application Use Conditions: The full environmental and/or operating range that the application is specified to function within. Typical Use Conditions: The normal environmental and/or operating range that the application is kno

27、wn to function within. This is a subset of the Application Use Conditions. Maximum Use Condition: This is the upper limit of an Application Use Condition. JEDEC Publication No. 149 Page 2 4 Derating process Simplistically, derating is a two step process. A “rated” stress value for the device is dete

28、rmined from the manufacturers specification, and then a reduced value is assigned for the application stress maximum. As stated in the introduction, derating can be employed to achieve various goals. The method of derating may need to be adjusted depending on the goal as well. Since reliability is d

29、etermined primarily from the use conditions the device encounters most of the time, derating for this purpose may be best achieved through a large margin from manufacturers specification limits, compared to typical use conditions. Conversely, if assurance of functional performance, not related to re

30、liability (i.e., for short, unusual use conditions), is the goal, a smaller margin from the manufacturers specification limits, compared to maximum use conditions, may be appropriate. In other cases, the difference between the typical and maximum use condition may be small such that these goals shou

31、ld be treated as the same. Here functionality and reliability should be evaluated at the maximum use condition and a margin set dependent on the customer needs and criticality of the application. NOTE 1 With modern CMOS circuits, it may be relatively straightforward to derate for speed, but not typi

32、cally so for functionality. In these cases, the published functionality limits should be used, independent from derating. NOTE 2 When applying derating to new technologies and packages, an equipment manufacturer needs to address many issues. This typically involves user qualification tests and analy

33、ses of the technology as assembled in a typical use configuration. These tests and analyses should show a level of robustness and margin above the actual expected use conditions. The user application qualification process is out of the scope of this document, however the results of such testing and

34、analysis can be used as a data point from which to derate from, with assistance from the component manufacturer. 4.1 Derating for reliability Operating conditions such as temperature, power consumption, operating voltage, and output current or fanout all have an impact on reliability. Most of these

35、impact reliability through failure mechanisms related to higher interconnect current densities, gate oxide field strength, or chip temperature. There are also package related concerns that are accelerated by temperature, such as the degradation of Au/Al intermetallics causing bond failures in plasti

36、c encapsulated devices containing certain flame retardant. Bromated epoxies release bromide when heated, which has the effect of accelerating intermetalic formation between the gold bond wires and the aluminum die bond pads1. Consideration is needed for the glass transition temperature of the encaps

37、ulant as well. 1 “Reliability Implications of Derating Leading Edge High Complexity Microcircuits”, S. Richard Biddle, Texas Instruments Inc., January 26, 2000. JEDEC Publication No. 149 Page 3 4.1 Derating for reliability (contd) Methodologies for evaluation of semiconductor reliability can be foun

38、d in JEP143 “Solid State Reliability Assessment and Qualification Methodologies”. These can be factored to use conditions from acceleration factors listed in the documents referenced within JEP143 and with assistance from the manufacturer. Items to be considered include both FIT rate versus temperat

39、ure and lifetime versus temperature. Figure 1 shows an example of FIT rate versus temperature. Consultation with the manufacturer is necessary for this information2. All of this should be factored with respect to the use operating conditions of the application. Since many of the failure mechanisms a

40、re related to operating temperature, this is used here as an example (also see Annex A for more guidance on thermal derating). In this respect, reliability is impacted by the time loading at various operating temperatures or time at temperature. In some cases, the highest known operating temperature

41、 is assumed to be constant resulting in a very conservative reliability estimate. More realistic estimates can be achieved through the use of a probability plot of time versus temperature. A conservative estimate can still be calculated using a temperature figure that contains significantly larger t

42、han 50% of the total time at temperature under this curve. For example, Figure 1 shows a mean use condition junction temperature of 55 C, and a standard deviation of 15 C. If the temperature 1 sigma from the mean is used in a reliability calculation, 84.1% of the total time at use condition is below

43、 that temperature. Assuming this use temperature of 70 C as a constant temperature could be one way of providing more realistic, yet conservative, reliability estimations, while providing a large margin below the manufacturers maximum specification limit of 120 C. 00.0050.010.0150.020.0250.030 5 10

44、15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120Temperature (TJ C)Probability0100200300400500600700800900FIT Rate+1 Sigma Mfrs RatingUse ConditionProbabilityFIT Rate(0.5eV Activation Energy Assumed)Figure 1 Application thermal environment and FIT rate plot 2 Manufacturers may c

45、ommunicate reliability and life information to customers in the form of a Quality Assurance Agreement (QAA), or similar document. Guidance from the manufacturer is necessary to extend the reliability or life data, provided in this documentation, through derating. JEDEC Publication No. 149 Page 4 4.1

46、 Derating for reliability (contd) Another example of a method for determining a mathematically appropriate derating margin involves using the RMS (square root of the sum of squares) result of the quantifiable condition (electrical, environmental, etc.) as the derated value. Derating to a RMS value c

47、an be appropriate and practical; especially when there are cumulative variances or other use condition data available. Significant operating time spent at higher temperatures will impact wearout mechanisms in semiconductor devices. JEDEC publication, JEP122 addresses many of these wearout failure me

48、chanisms and provides general models for estimating life for various conditions. 4.2 Derating for functionality Applications often have a relatively narrow range of “normal” operating conditions as compared to the maximum use conditions that may compose a very small percentage of the total applicati

49、on life. These maximum conditions are typically due to specific events like breakdown of the local area cooling system or influence of unusual weather conditions. Thus, reliability may not be significantly impacted by these maximum conditions. In such cases, the functionality of a device is required, but can be evaluated independently from reliability. The major difference is that the margin under the manufacturer rated maximum conditions can be smaller than that used for derating for reliability. Microcircuits generally slow down at higher temperatures. Derati