DLA SMD-5962-98627 REV A-2007 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED SCHOTTKY TTL DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS W CLEAR AND PRESET MONOLITHIC SILICON《微型电路 线型 双极改进型肖.pdf

《DLA SMD-5962-98627 REV A-2007 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED SCHOTTKY TTL DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS W CLEAR AND PRESET MONOLITHIC SILICON《微型电路 线型 双极改进型肖.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-98627 REV A-2007 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED SCHOTTKY TTL DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS W CLEAR AND PRESET MONOLITHIC SILICON《微型电路 线型 双极改进型肖.pdf（12页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements. Editorial changes throughout. - gap 07-03-12 Robert M. Heber REV SHET REV SHET REV STATUS REV A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Larry E. Shaw DEFENSE SUPPLY

2、CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Lee J. Surowiec COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Raymond Monnin MICROCIRCUIT, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY, TTL, DUAL POSITIVE- AND AGENCIES OF THE DEPARTM

3、ENT OF DEFENSE DRAWING APPROVAL DATE 98-06-30 EDGE-TRIGGERED D-TYPE FLIP-FLOPS W/CLEAR AND PRESET, MONOLITHIC SILICON AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-98627 SHEET 1 OF 11 DSCC FORM 2233 APR 97 5962-E071-07 Provided by IHSNot for ResaleNo reproduction or networking permitted with

4、out license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98627 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classe

5、s Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the

6、following example: 5962 - 98627 01 Q C X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MI

7、L-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device t

8、ype(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54AS74A Dual positive-edge-triggered D-type flip-flops w/clear and preset 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows:

9、Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s

10、) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style C GDIP1-T14 or CDIP2-T14 14 Dual-in-line 2 CQCC1-N20 20 Square chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-3853

11、5, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98627 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute max

12、imum ratings. 1/ Supply voltage (VCC) +7.0 V dc Maximum power dissipation (PD) 2/ 112 mW Input voltage (VI) . +7.0 V dc Storage temperature range . -65C to +150C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) +175C Case operating temperature range (TC) -55C to +

13、125C 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc High-level input voltage (VIH) . +2.0 V minimum Low-level input voltage (VIL) +0.8 V maximum High-level output current (IOH) . -2.0 mA maximum Low-level output current (IOL) 20 mA maximum Clock Frequency (fc

14、lock) 0-90 MHz Pulse duration (tw) : PRE or CLR low . 4 ns minimum CLK high 4 ns minimum CLK low . 5.5 ns minimum Setup time before CLK (tsu) : Data: 4.5 ns minimum PRE or CLR inactive: . 2 ns minimum Hold time after CLK (th) Data . 0 ns minimum Case operating temperature (TC) -55C to +125C 2. APPLI

15、CABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTM

16、ENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK

17、-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or www.dodssp.daps.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphi

18、a, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtai

19、ned. _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Maximum power dissipation is defined as VCCx ICC, and must withstand the added PDdue to short circuit test; e.g.,

20、 IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98627 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The i

21、ndividual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The indiv

22、idual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and

23、herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Function table. The function ta

24、ble shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics and postirradiation parameter

25、limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgr

26、oups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to sp

27、ace limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with

28、 MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For

29、device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an appr

30、oved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein o

31、r for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits del

32、ivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. Fo

33、r device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. D

34、evice class M devices covered by this drawing shall be in microcircuit group number 10 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98627 DEFENSE SUPPLY CENTER COLUMBUS COL

35、UMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test SymbolConditions -55C TC +125C Group A subgroups Limits 1/ Unit unless otherwise specified Min Max Input clamp voltage VIKVCC= 4.5 V, II= -18 mA 1, 2, 3 -1.2 V High-level outpu

36、t voltage VOHVCC= 4.5 V to 5.5 V, VIH= 2 V, IOH= -2 mA, VIL= 0.8 V 1, 2, 3 VCC-2 V Low-level output voltage VOLVCC= 4.5 V, VIH= 2 V, IOL= 20 mA, VIL= 0.8 V 0.5 V Input current IIVCC= 5.5 V, VI= 7 V 1, 2, 3 0.1 mA High-level input current CLK or D IIHVCC= 5.5 V, VI= 2.7 V 1, 2, 3 20 A PRE or CLR 40 L

37、ow-level input current CLK or D IILVCC= 5.5 V, VI= 0.4 V 1, 2, 3 -0.5 mA PRE or CLR -1.8 Short circuit output current 2/ IOSVCC= 5.5 V, VO= 2.25 V 1, 2, 3 -30 -112 mA Supply current 3/ ICCVCC= 5.5 V, Outputs open, All inputs at 4.5 V 1, 2, 3 16 mA Functional test See 4.4.1b 7, 8A, 8B Switching frequ

38、ency fMAX9, 10, 11 90 MHz Propagation delay time, low-to-high level output From PRE or CLR to Q or Q tPLHRL= 500 , CL= 50 pF VCC= 4.5V to 5.5 V, TC= min to max 3/ 9, 10, 11 2 9 ns CLK to Q or Q tPLH9, 10, 11 2.5 10 ns Propagation delay time, high-to-low level output From PRE or CLR to Q or Q tPHL9,

39、10, 11 2.5 11.5 ns CLK to Q or Q tPHL9, 10, 11 3.5 10.5 ns 1/ For negative and positive voltage and current values, the sign designates the potential difference to GND and the direction of current flow, respectively, and the absolute value of the magnitude, not the sign, is relative to the minimum a

40、nd maximum limits, as applicable, listed herein. 2/ ICCis measured with D, CLK, and PRE grounded, then with D, SLK, and CLR grounded. 3/ Load circuits and voltage waveforms are shown in Figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDA

41、RD MICROCIRCUIT DRAWING SIZE A 5962-98627 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 Device type 01 Case outlines C 2 Terminal number Terminal symbol 1 1 CLR NC 2 1D 1 CLR 3 1CLK 1D 4 1 PRE 1CLK 5 1Q NC 6 1 Q 1PRE 7 GND NC 8 2 Q 1Q 9 2Q 1

42、Q 10 2 PRE GND 11 2CLK NC 12 2D 2 Q 13 2 CLR 2Q 14 VCC2 PRE 15 NC 16 2CLK 17 NC 18 2D 19 2 CLR 20 VCCNC = No connection FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98627 DE

43、FENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H 1/ H 1/ H H H H L H H L L H H H L X Q0Q0L = LowH = High X = Doesnt matter NOTE: 1. The output levels in this configuration are not

44、specified to meet the minimum levels for VOHif the lows at PRE and CLR are near VILmaximum. Furthermore, this configuration is non-stable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. FIGURE 2. Function table. NOTE: Positive logic FIGURE 3. Logic Diagram Provide

45、d by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98627 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 NOTES: 1. CLincludes probe and jig capacitance (See Table

46、 1). 2. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, tr= tf= 2 ns, duty cycle = 50%. 3. The outputs are measured one at a time with one transition per measurement. FIGURE 4. Test circuit and timing waveforms. Provided by IHSNot for ResaleNo reproductio

47、n or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98627 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 9 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspect

48、ion procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technolo