DLA SMD-5962-01503 REV C-2013 MICROCIRCUIT HYBRID CUSTOM FIELD EFFECT TRANSISTORS 600 VOLT OR 500 VOLT WITH GATE PROTECTION.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added device type 02. Added vendor cages U4388, 51651, and 57363. Added Resistance junction-to-case (RJC) to paragraph 1.3. Added paragraphs 3.2.7, 4.3.3.1, and 5.1.2. Changed paragraphs 1.2, 1.2.2, 1.2.3, 1.3, 1.4, 2.1, 3.1, 3.2.6, 4.1, 4.1.1, 4

2、.2, 4.3.3, and 4.3.6. Table I; made changes to the the tests VGS(th)1, VGS(th)2, VGS(th)3, RDS(ON)1, RDS(ON)2, IDSS1, td(ON), tr, td(off), and tf. Made changes to Figure 1. -sld 05-12-07 Raymond Monnin B Correct paragraph 1.3, Resistance, junction to case, change 0.7C/W to 1.2C/W. -gz 11-08-01 Charl

3、es F. Saffle C Table I: For the test td(off)changed the max limit for device type 02 from “200 ns“ to “230 ns“. -sld 13-09-16 Charles F. Saffle REV SHEET REV C C SHEET 15 16 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Steve L. Dunc

4、an DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Michael Jones COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A APPROVED BY Raymond Monnin MICROCIRCUIT, HYBRID, CUSTOM

5、, FIELD EFFECT TRANSISTORS, 600 VOLT OR 500 VOLT, WITH GATE PROTECTION DRAWING APPROVAL DATE 01-01-18 REVISION LEVEL C SIZE A CAGE CODE 67268 5962-01503 SHEET 1 OF 16 DSCC FORM 2233 APR 97 5962-E571-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-

6、STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01503 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents five product assurance classes as defined in paragraph 1.2.3 and MIL-PRF-38534. A choice of case outlines and lead

7、 finishes which are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of radiation hardness assurance levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 - 01503 01 H X X Federal RHA Device Device Case Lead st

8、ock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 Radiation hardness assurance (RHA) designator. RHA marked devices shall meet the MIL-PRF-38534 specified RHA levels and shall be marked with the a

9、ppropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Vendor similar PIN Circuit function 01 12786, NHI-1670, MSK1665H Field Effect Transistor, 600 V, N-channel, with gate protection circuitry

10、02 13023, NHI-1668, MSK1666H Field Effect Transistor, 500 V, N-channel, with gate protection circuitry 1.2.3 Device class designator. This device class designator shall be a single letter identifying the product assurance level. All levels are defined by the requirements of MIL-PRF-38534 and require

11、 QML Certification as well as qualification (Class H, K, and E) or QML Listing (Class G and D). The product assurance levels are as follows: Device class Device performance documentation K Highest reliability class available. This level is intended for use in space applications. H Standard military

12、quality class level. This level is intended for use in applications where non-space high reliability devices are required. G Reduced testing version of the standard military quality class. This level uses the Class H screening and In-Process Inspections with a possible limited temperature range, man

13、ufacturer specified incoming flow, and the manufacturer guarantees (but may not test) periodic and conformance inspections (Group A, B, C, and D). E Designates devices which are based upon one of the other classes (K, H, or G) with exception(s) taken to the requirements of that class. These exceptio

14、n(s) must be specified in the device acquisition document; therefore the acquisition document should be reviewed to ensure that the exception(s) taken will not adversely affect system performance. D Manufacturer specified quality class. Quality level is defined by the manufacturers internal, QML cer

15、tified flow. This product may have a limited temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01503 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 AP

16、R 97 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 4 or 10 1/ Hybrid package 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38534 and figure 1 herein. 1.3

17、Absolute maximum ratings. 2/ Power dissipation (PD) 3/ 25 W Breakdown voltage, drain to source (V(BR)VSS): Device type 01 600 V dc minimum Device type 02 500 V dc minimum Gate to source voltage range (VGS) -0.5 V dc to +14.2 V dc Source drain diode voltage (VDS): Device type 01 600 V dc Device type

18、02 500 V dc Drain current maximum: 4/ Device type 01 6.0 A dc Device type 02 8.0 A dc Pulsed drain current maximum: 5/ Device type 01 15.0 A dc Device type 02 20.0 A dc Junction temperature (TJ) +150C Isolation voltage (VISO) 70000 ft altitude: Device type 01 600 V dc Device type 02 500 V dc Resista

19、nce, junction to case (RJC) 6/ 1.2C/W Lead temperature (TL): 0.063 inches (1.60 mm) from case for 10 seconds +300C Case operating temperature range (TC) -55C to +125C Storage temperature range -55C to +150C 1.4 Recommended operating conditions. Gate to source voltage, threshold range (VGS(th)1) +2.0

20、 V dc to +4.0 V dc Source current (IS): Device type 01 3.0 A dc steady state, 7.5 A pulsed Device type 02 4.0 A dc steady state, 10.0 A pulsed Drain current (ID1) TC= +25C: Device type 01 3.0 A dc steady state, 7.5 A pulsed Device type 02 4.0 A dc steady state, 10.0 A pulsed 1/ For the 10 lead packa

21、ge, configuration B in figure 1, pins 1 through 4 are tied together for the DRAIN (pin 1) and pins 5 through 8 are tied together for the SOURCE (pin 2). 2/ Stresses above the absolute maximum ratings may cause permanent damage to the device. Extended operation at the maximum levels may degrade perfo

22、rmance and affect reliability. 3/ Derate linearly 0.16 W/C for TC +25C. PD= TJ- TC/ RJC.4/ Repetitive rating, pulse width limited by maximum junction temperature. 5/ Pulsed. Conditions for pulse measurement shall be as specified in section 4 of MIL-STD-750. 6/ When tested per method 3161of MIL-STD-7

23、50, with the following conditions: IM= 10 mA, IH=3 A, tH= 15 seconds, VH= 8.4 V, tMD= 100 s, and tSW= 10 s. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01503 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-399

24、0 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents

25、 are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38534 - Hybrid Microcircuits, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-750 - Test Method Standard for Semiconductor Devices. MIL-STD-883 - Test Method Standard Microcircuits. MIL-S

26、TD-1835 - Interface Standard for Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil/ or from the Standar

27、dization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicita

28、tion. ELECTRONICS INDUSTRIES ALLIANCE (EIA) JESD22-A101 - Steady State Temperature Humidity Bias Life Test. JESD22-A110 - Test Method A110 Highly Accelerated Temperature and Humidity Stress Test (HAST). JESD22-A113 - Test Method A113 Preconditioning of Plastic Surface Mount Devices Prior to Reliabil

29、ity Testing. JESD22-B101 - Test Method B101 External Visual. J-STD-033 - Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices. (Copies of these documents are available online at http:/www.jedec.org/ or from the Electronics Industries Alliance, 2500 Wils

30、on Boulevard, Arlington, VA 22201-3834). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific ex

31、emption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and K shall be in accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 shall include the performance of all tests herein or as designated in the devic

32、e manufacturers Quality Management (QM) plan or as designated for the applicable device class. The manufacturer may eliminate, modify or optimize the tests and inspections herein, however the performance requirements as defined in MIL-PRF-38534 shall be met for the applicable device class. In additi

33、on, the modification in the QM plan shall not affect the form, fit, or function of the device for the applicable device class. Class D parts are defined by the requirements as specified in 4.3.6 and herein. Class D, non-hermetic parts supplied to this drawing shall meet the requirements of this draw

34、ing however, tests which are relevant to non-hermetic technologies should be used. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01503 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET

35、5 DSCC FORM 2234 APR 97 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38534 and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections

36、. The terminal connections shall be as specified on figure 2. 3.2.3 Schematic diagram. The schematic diagram shall be as specified on figure 3. 3.2.4 Switching waveform. The switching waveform shall be as specified on figure 4. 3.2.5 Rework. The rework requirements shall be in accordance with MIL-PR

37、F-38534 except that the limits on polymer element replacement shall not apply as long as the substrate material is not damaged and all the bond pads are inspected in accordance with documented inspection requirements prior to the installment of the replacement components. 3.2.6 Unique circuit elemen

38、ts. The circuit elements in the following table are unique to this application and are not adequately verifiable by testing the completed part. Substitutions, except as noted below, are not allowed: Device types Reference Designator as specified on Figure 3 Part Number (Source) 01 Q1 APT6040DN (0DY7

39、4) Q1 - (substitute) APT6040DNC (0DY74) See Note 02 Q1 APT5025DN (0DY74) Q1 - (substitute) APT5025DNC (0DY74) See Note Note: The Q1 (substitute) part number has a silicon carbide coating for improved moisture resistance. 3.2.7 High voltage spacing details. These parts are intended for high altitude,

40、 high voltage applications in extreme environmental conditions. Internal conductors over 200 V shall have a .007 inch minimum spacing between any other conductive surface. Layout dimensions shall be available for user verification of dimensions. If the internal cavity contains helium, the helium sha

41、ll be 15 percent by volume maximum. Critical spacing for external dimensions shall be as defined in figure 1. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full specified

42、operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The d

43、evice shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers vendor similar PIN may also be marked. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01503 DLA LAND AND MARITIME COLUM

44、BUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol 1/ Conditions 1/ -55C TC+125C unless otherwise specified Group A subgroups Device types Limits Unit Min Max Breakdown voltage, drain to source V(BR)DSSMethod 3407, Bias co

45、ndition C, VGS= 0 V dc, ID= 250 A dc 1 01 600 V dc 02 500 Gate to source voltage (threshold) VGS(th)1Method 3403, VDS= VGS, ID= 1.0 mA dc 1 All 2.0 4.0 V dc VGS(th)22 1.0 VGS(th)33 5.0 Gate Current IGSS1Method 3411, VGis applied with respect to VGATE_RTN, VDS= 0, VGS= +10 V dc 1,2,3 All 0.9 1.1 mA G

46、ate Protection VGZMethod 3411, VGis applied with respect to VGATE_RTN, VDS= 0, IG= 10 mA dc 1,2,3 All 14.2 18.2 V Method 3411, VGis applied with respect to VGATE_RTN, VDS= 0, IG= -2 mA dc -1.5 -0.3 Static drain to source “on“ state resistance RDS(ON)1Method 3421, Condition A, Pulsed, VGS= 10 V dc, (

47、ID= 3.0 A dc for device type 01) and (ID= 4.0 A dc for device type 02) 1 01 0.425 02 0.26 RDS(ON)22 01 0.9 02 0.52 Forward voltage (source drain diode) VSDMethod 4011, VGS= 0 V dc, IF= 1.0 A dc 1 All 1.3 V dc Drain Current IDSS1Method 3413, Bias condition C, VGS= 0 V dc, VDS= 100% V(BR)DSS1 All 250

48、A dc IDSS2Method 3413, Bias condition C, VGS= 0 V dc, VDS= 80% V(BR)DSS2 1000 Turn on delay time td(ON)Method 3472, RG = 6 , (ID= 1.5 A for device type 01) and ( ID= 2.0 A for device type 02), VGS= 15 V dc, VDD= 50 percent of V(BR)DSS, RL= VDD/ID, See figure 4 9 01 35 ns 02 40 Rise time tr01 35 ns 02 40 Turn off delay time td(off)01 200 ns 02 230 Fall time tfAll 140 ns 1/ Symbol definitions, methods, and conditions are in accordance with MIL-STD-750. Provided by IHSNot for ResaleNo reproduction or networ