DLA SMD-5962-01502 REV B-2007 MICROCIRCUIT DIGITAL CMOS RADIATION HARDENED MICROPROCESSOR MONOLITHIC SILICON《单片硅数字微电路 CMOS 辐射硬化微处理器》.pdf

《DLA SMD-5962-01502 REV B-2007 MICROCIRCUIT DIGITAL CMOS RADIATION HARDENED MICROPROCESSOR MONOLITHIC SILICON《单片硅数字微电路 CMOS 辐射硬化微处理器》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-01502 REV B-2007 MICROCIRCUIT DIGITAL CMOS RADIATION HARDENED MICROPROCESSOR MONOLITHIC SILICON《单片硅数字微电路 CMOS 辐射硬化微处理器》.pdf（37页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update boilerplate to MIL-PRF-38535 requirements. - LTG 01-03-28 Thomas M. Hess B Update boilerplate to current MIL-PRF-38535 requirements. - CFS 07-05-09 Thomas M. Hess REV B B SHET 35 36 REV B B B B B B B B B B B B B B B B B B B B SHEET 15 16 1

2、7 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV B B B B B B B B B B B B B B REV STATUS OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Larry T. Gauder CHECKED BY Thanh V. Nguyen DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil APPROVED BY

3、 Thomas M. Hess DRAWING APPROVAL DATE 00-10-31 MICROCIRCUIT, DIGITAL, CMOS, RADIATION HARDENED MICROPROCESSOR, MONOLITHIC SILICON SIZE A CAGE CODE 67268 5962-01502 STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A RE

4、VISION LEVEL B SHEET 1 OF 36 DSCC FORM 2233 APR 97 5962-E376-07Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-01502 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM

5、 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PI

6、N). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 H 01502 01 Q X X Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) des

7、ignator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specifie

8、d RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 UT1750AR-12 MHz Radiation hardened microprocessor, 12-MHz operatin

9、g frequency 02 UT1750AR-16 MHz Radiation hardened microprocessor, 16-MHz operating frequency 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to

10、 the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptiv

11、e designator Terminals Package style X CMGA7-P145 145 1/ Pin grid array Y CQCC1-F132 132 Flat pack, unformed leads 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. _ 1/ Pin D4 is an index pin.Provided by I

12、HSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-01502 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ DC supply voltage (VDD) -0.3 V

13、 to +7.0 V Voltage on any pin (VI/O) -0.3 V to VDD+0.3 V DC input current (II) . 10 mA Storage temperature (TSTG) . -65C to +150C Latchup immunity (ILU) . 150 mA 2/ Maximum power dissipation (PD) . 600 mW Maximum junction temperature (TJ) . +175C Thermal resistance, junction-to-case (JC) . 10C/W 2/

14、1.4 Recommended operating conditions. DC supply voltage (VDD) . 4.5 V to 5.5 V Temperature range (TC) -55C to +125C DC input voltage (VIN). 0 V to VDD1.5 Radiation features. Total dose (Dose rate = 50 300 Rads(Si)/s) 1 x 106Rads(Si) Single event phenomenon (SEP) effective linear energy threshold, no

15、 upsets or latchup (see 4.4.4.4) 55 MeV/(mg/cm2) 3/ Dose rate upset (20 ns pulse). 4/ Dose rate latchup . 4/ Dose rate survivability. 4/ Neutron irradiation 1 X 1014neutron/cm23/ 1.6 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-88

16、3, test method 5012) 83.7 percent 2/ _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Test per MIL-STD-883, method 1012. 3/ Limits are guaranteed by design or process

17、but not production tested unless specified by the customer through the purchase order or contract. 4/ When characterized as a result of the procuring activities request, the condition will be specified. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,

18、-SIZE A 5962-01502 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part o

19、f this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS

20、 MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available onli

21、ne at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified he

22、rein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation or contract. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of S

23、emiconductor Devices (Copies of these documents are available online at http:/www.astm.org or from ASTM International, 100 Barr Harbor Drive, P.O. Box C700, West Conshohocken, PA 19428-2959) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited

24、 herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance w

25、ith MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-

26、38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for d

27、evice class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 and figure 1 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.2.4 Test circuit and timing

28、 waveforms. The test circuit and timing waveforms shall be as specified on figure 4. 3.2.5 Radiation exposure connections. The radiation exposure connections shall be as specified on figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 59

29、62-01502 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristic

30、s and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in

31、table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on th

32、e device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certificatio

33、n mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-

34、38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of comp

35、liance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3

36、.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device

37、 class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option

38、 to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group numb

39、er 105 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-01502 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE IA.

40、Electrical performance characteristics. Limits Test Symbol 1/ Test conditions 2/ -55C TC +125C unless otherwise specified Group A subgroups Device Type Min Max Unit Low level input voltage, TTL inputs 3/ VIL10.8 Low level input voltage, OSC inputs 3/ VIL21, 2, 3 All 1.2 V High level input voltage, T

41、TL inputs 3/ 4/ VIH12.0 High level input voltage, OSC inputs 3/ VIH21, 2, 3 All 3.6 V IOH= -400 A 2.4 High level output voltage, TTL outputs VOH1IOH= -800 A 5/ 1, 2, 3 All 2.4 High level output voltage, OSC outputs VOH2IOH= -100 A 1, 2, 3 All 3.5 V IOL= 3.2 Ma 0.4 Low level output voltage, TTL outpu

42、ts VOL1IOL= 6.4 mA 5/ 1, 2, 3 All 0.4 Low level output voltage, OSC outputs VOL2IOL= 100 A 1, 2, 3 All 1.0 V Input leakage current, inputs without resistors IIN1VIN= VDDor VSS-10 10 Input leakage current, inputs with pull-up resistors IIN2VIN= VSS-900 -80 Input leakage current, inputs with pull-down

43、 resistors IIN3VIN= VDD1, 2, 3 All 80 900 A -10 +10 Three-state output leakage current IOZVO= VDDor VSS 1, 2, 3 All -20 5/ +20 5/ A VDD= 5.5 V, VO= 0 V to VDD-100 100 Short circuit output current 6/ 7/ IOSVDD = 5.5 V, VO= 0 V 1, 2, 3 All -200 5/ 200 5/ mA f = 12 MHz, CL= 50 pF 50 Average operating c

44、urrent 6/ 8/ IDDf = 16 MHz, CL= 50 pF 1, 2, 3 All 75 mA Quiescent current 9/ QIDD1, 2, 3 All 1 mA Input capacitance CIN4 All 10 pF Output capacitance COUTAll 15 pFBidirect I/O capacitance CI/Of = 1 MHz at 0 V See 4.4.1c 4 All 20 pF Functional tests 3/ See 4.4.1b 7, 8 All See footnotes at end of tabl

45、e. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-01502 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristic

46、s Continued. Limits Test Symbol 1/ Test conditions 2/ -55C TC +125C unless otherwise specified Group A subgroups Device type Min Max Unit I/O READ CYCLE 01 0 42 OSCIN low to STATE1 high t34a* 9, 10, 11 02 0 33 01 0 39 OSCIN low to STATE1 low t34b* 9, 10, 11 02 0 33 01 0 51 OSCIN low to AS active t34

47、c* 9, 10, 11 02 0 42 01 0 50 OSCIN low to AS inactive t34d* 9, 10, 11 02 0 38 01 - 50 SCIN low to AS high Z t34e 9, 10, 11 02 - 38 01 0 54 OSCIN low to DS inactive t34f* 9, 10, 11 02 0 45 01 0 37 OSCIN low to DS active t34g* 9, 10, 11 02 0 35 01 0 50 OSCIN high to DS inactive t34h* 9, 10, 11 02 0 38

48、 01 - 50 OSCIN low to DS high Z t34i 9, 10, 11 02 - 38 01 0 54 OSCIN low to R/ WR active t34j 9, 10, 11 02 0 41 01 - 50 OSCIN low to R/ WR high Z t34k 9, 10, 11 02 - 38 01 0 51 OSCIN low to M/IO low t34l* 9, 10, 11 02 0 42 01 0 73 OSCIN high to M/IO high t34m* 9, 10, 11 02 0 55 01 - 50 OSCIN low to M/IO high Z t34n 9, 10, 11 02 - 38 01 0 54 OSCIN low to OP/IN high t34o* See figure 4. 9, 10, 11 02 0 41 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without li