DLA DSCC-VID-V62 12601-2012 MICROCIRCUIT DIGITAL-LINEAR ENHANCED LOW INPUT VOLTAGE MODE SYNCHRONOUS BUCK CONTROLLER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original d

2、ate of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL-LINEAR, ENHANCED, LOW INPUT VOLTAGE MODE SYNCHRONOUS BUCK CONTROLLER, MONOLITHIC SILICON 12-12-14 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12601 REV PAGE 1 OF 11 AMSC N/A 5962-V034-13 Provided by

3、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12601 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance enhanced, low input voltage mo

4、de synchronous buck controller microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item

5、 on the engineering documentation: V62/12601 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TPS40021-EP Enhanced, low input voltage mode synchronous buck controller 1.2.2 Case outline(s).

6、The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 JEDEC MO-153 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot so

7、lder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12601 REV PAGE 3 1.3 Absolute maximum ratin

8、gs. 1/ Input voltage range, (VIN): SS/SD, VDD, PVDD, OSNS -0.3 V to 6.0 V BOOT2, BOOT1 . VSW+ 6.0 V SW . -3.0 V to 10.5 V SWT (SW transient 50 ns) -5.0 V FB, ILIM . -0.3 V to 6.0 V Output voltage range, (VOUT): COMP, PWRGD, RT -0.3 V to 6.0 V Sink current, (IS): PWDGD 10 mA Maximum junction temperat

9、ure, (TJ) . 150C Storage temperature range (Tstg) . -65C to 150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260C 1.4 Thermal characteristics. Thermal resistance Thermal metric 2/ Case outline X Units Junction to ambient thermal resistance, JA3/ 38.3 C/W Junction to case (top) therm

10、al resistance, JCtop4/ 28 Junction to board thermal resistance, JB5/ 9 Junction to top characterization parameter, JT6/ 0.4 Junction to board characterization parameter, JB7/ 8.9 Junction to case (bottom) thermal resistance, JCbot8/ 2.9 1.5 Recommended operating conditions. Input voltage, (VIN) 2.25

11、 V to 5.5 V Operating temperature range, (TJ) -55C to 125C 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “r

12、ecommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. 2/ For more information about traditional and new thermal metr

13、ics, see manufacturer data. 3/ The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-k-board, as specified in JESD51-7, in an environment described in JESD51-2a. 4/ The junction to case (top) thermal resistance is obtained by simula

14、ting a cold plate test on the package top. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 5/ The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temper

15、ature, as described in JESD51-8. 6/ The junction to top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 7/ The junction to board ch

16、aracterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 8/ The junction to case (bottom) thermal resistance is obtained by simulating a cold

17、plate test on the exposed (power) pad. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE ID

18、ENT NO. 16236 DWG NO. V62/12601 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) JESD51-7

19、High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages JESD51-8 Junction-to-board thermal resistance Theta-JB or RJB(Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, A

20、rlington, VA 22201-2107). AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) STANDARD ANSI SEMI STANDARD G30-88 - Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to the American National Standards Institute, Semiconductor E

21、quipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE

22、code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical

23、performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2

24、 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Internal block diagram. The internal block diagram shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHI

25、O SIZE A CODE IDENT NO. 16236 DWG NO. V62/12601 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ Limits Unit Min Max Input Supply Input voltage range VDD2.25 5.50 V PVDD pin voltage VPVDDVDD= 3.3 V 5.20 V Switching current IDD500 KHz, No load on HDRV, LDRV 5.0

26、 mA Quiescent current FB = 0.8 V 3.0 Shutdown current SS/SD = 0 V, Outputs OFF 1.0 Minimum on voltage VUVLO1.95 2.15 V Hysteresis 72 200 mV Oscillator Accuracy fOSC2.25 V VDD 5.00 V, RT = 69.8 k 405 575 kHz 2.25 V VDD 5.00 V, RT = 34.8 k 740 1100 Ramp voltage VRAMPVPEAK- VVAL0.80 1.07 V Ramp valley

27、voltage VVAL0.24 0.41 PWM Maximum duty cycle dMAXVOSNS= VDD, RT= 34.8 k, VDD= 3.3 V, FB = 0 V 85 % VOSNS= VDD, RT= 70 k, VDD= 5.0 V, FB = 0 V 90 % Minimum duty cycle dMIN0 TYP % Minimum HDRV on-time 3/ tMIN250 TYP ns Error Amplifier Feedback input voltage VFB2.25 V VDD 5.00 V 0.683 0.701 V Input bia

28、s current IBIAS130 nA High level output voltage VOHIOH= 0.5 mA, VFB= GND 2.0 V Low level output voltage VOLIOL= 0.5 mA, VFB= VDD0.15 High level output source current IOHVFB= GND 2.7 mA Low level output sink current IOLVFB= VDD3 Gain bandwidth 4/ GBW10 TYP MHz Open loop gain AOL53 dB Current limit Cu

29、rrent limit sink current ISINK2.25 V VDD 5.00 V, RT= 69.8 k 165 215 A Current limit offset voltage VOS-20 20 mV Minimum HDRV on time in overcurrent tONVDD= 3.3 V 300 ns Switching leading edge blanking pulse time 4/ 140 TYP Soft start cycles tSS6 TYP cycles Current limit input voltage range VILIM2 VD

30、DV Soft start Soft start source current ISSOutputs = OFF 2.0 5.4 A See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12601 REV PAGE 6 TABLE I. El

31、ectrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ Limits Unit Min Max Shutdown Shutdown threshold voltage VSD0.2 0.29 V Device enable threshold voltage VEN0.25 0.32 Output Driver High side driver pull up resistance RHDHIV(BOOT1) V(SW)= 3.3 V, ISOURCE= 100 mA 1.0 5.0 High

32、 side driver pull down resistance RHDLOV(BOOT1) V(SW)= 3.3 V, ISINK= 100 mA 0.7 3.0 Low side driver pull up resistance RLDHIPVDD= 3.3 V, ISOURCE= 100 mA 1.0 5.0 Low side driver pull down resistance RLDLOPVDD= 3.3 V, ISINK= 100 mA 0.41 1.50 Low side driver rise time tLRISECLOAD= 1 nF 35 ns Low side d

33、river fall time tLFALL25 High side driver rise time tHRISE35 High side driver fall time tHFALL25 Thermal Shutdown Shutdown temperature 4/ 165 TYP C Hysteresis 4/ 15 TYP Charge Pump RDS(on)VDD to BOOT2 RVB2VDD= 5.0 V, ISOURCE= 10 mA 2.8 10.4 RDS(on)BOOT2 to PVDD RB2PVDD= 5.0 V, ISOURCE= 10 mA 2.8 8.4

34、 RDS(on)PVDD to BOOT1 RPB1VDD= 5.0 V, ISOURCE= 10 mA 2.9 8.9 Power Good Pull down voltage VOSNS= 0.8 V, IPWRGD= 0.5 mA, VDD= 3.3 V 50 140 mV Output sense high to power good low delay time 0.7 V VOSNS 0.8 V, IPWRGD= 0.5 mA, VDD= 3.3 V 6 14 s Output sense low to power good low delay time 0.6 V VOSNS 0

35、.7 V, IPWRGD= 0.5 mA, VDD= 3.3 V 6 14 Shut down high to power good high delay time VOSNS= 0.7 V, IPWRGD= 0.5 mA, VDD= 3.3 V, 0.0 V VSS/SD 0.4 V 2 6 Shut down low to power good low delay time 0.5 3.0 Output sense high to nominal to power good high delay time 0.7 V VOSNS 0.8 V, IPWRGD= 0.5 mA, VDD= 3.

36、3 V 140 1000 ns Output sense high to nominal to power good high delay time 0.6 V VOSNS 0.7 V, IPWRGD= 0.5 mA, VDD= 3.3 V 140 1000 Transient comparators Overvoltage output threshold voltage VOVReference VFB23 35 mV Hysteresis 8 22 Undervoltage output threshold voltage VUV-37 -25 Hysteresis 8 22 OSNS

37、minimum disable voltage VDISReferenced to VDD0.5 V See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12601 REV PAGE 7 TABLE I. Electrical perform

38、ance characteristics - Continued. 1/ Test Symbol Conditions 2/ Limits Unit Min Max Synchronization Synchronization enable low threshold voltage VENSY0.7 V Synchronization current limit enable threshold voltage VBLNKReferenced to VDD -0.7 Minimum synchronization input pulse width tMIN50 ns Predictive

39、 Delay Sense voltage to modulate delay VSWP-200 TYP mV Maximum delay modulation tLDHDLDRV OFF to HDRV ON 40 90 ns Counter delay/bit time 2.5 6.2 Maximum delay modulation tHDLDHDRV OFF to LDRV ON 80 TYP Counter delay/bit time 5 TYP Rectifier Zero current comparator Zero current blanking time 4/ tZBLN

40、K150 TYP ns 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the abs

41、ence of specific parametric testing, product performance is assured by characterization and/or design. 2/ TJ= -55C to 125C, TJ= TA, VDD= 5.0 V (unless otherwise noted). 3/ Operation below the minimum on time could result in overlap of the HDRV and LDRV outputs. 4/ Specified by design. Not production

42、 tested. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12601 REV PAGE 8 Case X e bE E1D816AA10.10 MSEE DETAIL ASEATINGPLANE0.10cL0-80.25(.010)GAGEPLANEDETAIL A9THERMALPAD1

43、Dimensions Symbol Millimeters Symbol Millimeters Min Max Min Max A 1.20 E 4.30 4.50 A1 0.05 0.15 E1 6.20 6.60 b 0.19 0.30 e 0.65 BSC c 0.25 TYP L 0.50 0.70 D 4.90 5.10 NOTES: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Body dimensions do not i

44、nclude mold flash or protrusions. Mold flash and protrusion shall not exceed 0.15 per side. 4. This package is designed to be soldered to a thermal pad on the board. Refer to manufacturer for information regarding recommended board layout. 5. See the additional figure in the manufacturer Product dat

45、a sheet for details regarding the exposed thermal pad features and dimensions. 6. Falls within JEDEC MO-153. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG

46、NO. V62/12601 REV PAGE 9 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 ILIM/SYNC 9 PWRGD 2 VDD 10 PGND 3 OSNS 11 LDRV 4 FB 12 PVDD 5 COMP 13 BOOT2 6 SS/SD 14 SW 7 RT 15 HDRV 8 SGND 16 BOOT1 FIGURE 2. Terminal connections. Terminal name Terminal number I/O Descripti

47、on BOOT1 16 I This pin provides a bootstrapped supply for the high side FET driver, enabling the gate of the high side FET to be driven above the input supply rail. Connect a capacitor from this pin to the SW pin. BOOT2 13 I This pin provides a secondary bootstrapping necessary for generation of PVD

48、D. Connect a capacitor from this pin to the SW. COMP 5 O Output of the error amplifier. refer to Electrical Characteristics table for loading constraints. FB 4 I Inverting input of the error amplifier. In normal operation, VFBis equal to the internal reference level of 690 mV. HDRV 15 O The gate drive output for the high side N-channel MOSFET switch is