DLA DSCC-VID-V62 09627 REV A-2009 MICROCIRCUIT DIGITAL RECEIVER MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY MM
2、 DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL RECEIVER, MONOLITHIC SILICON 09-05-20 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09627 REV PAGE 1 OF 13 AMSC N/A 5962-V055-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IH
3、S-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09627 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance digital receiver microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item
4、 Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/09627 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2
5、.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TFP401A-EP Digital receiver 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 100 MS-026 Plastic Quad Flatpack 1.2.3 Lead finishes. The
6、 lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without licen
7、se from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09627 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage, (DVDD, AVDD, OVDD, PVDD) -0.3 V to 4.0 V Input voltage, logic/analog signals . -0.3 V to 4.0 V Storage temperature range (TSTG) . -
8、65C to 150C 2/ Operating temperature range . -55C to 125C Case temperature for 10 s . 260C Lead temperature (1.6 mm (1/16 in) from the case for 10 s) . 260C Maximum package power dissipation: Soldered . 4.3 W 3/ Not soldered . 2.7 W 4/ ESD protection, all pins 25 kV, Human Body model JEDEC latch up
9、(EIA/JESD78) 100 mA 1.4 Recommended operating conditions. 5/ Supply voltage VDD, (DVDD, AVDD, PVDD, OVDD) . 3.0 V to 3.6 V Pixel time, (tpix) . 6.06 ns to 40 ns 6/ Single ended analog input termination resistance, . 45 to 75 Operating free air temperature, (TA) . -55C to 125C 1/ Stresses beyond thos
10、e listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rate
11、d conditions for extended periods may affect device reliability. 2/ Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. 3/ Specified with the bond pad on the backside of the package soldered to a 2 oz. C
12、u plate PCB thermal plane. Specified at maximum allowed operating temperature, 70C. 4/ The bond pad on the backside of the package is not soldered to a thermal plane. Specified at maximum allowed operating temperature, 70C. 5/ Use of this product beyond the manufacturers design rules or stated param
13、eters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 6/ tpixis the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK is equal to tpixwhen in 1-pixel/clock mo
14、de and 2tpixwhen in 2-pixel/clock mode. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09627 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standa
15、rd Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer
16、s part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical
17、characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.
18、5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Function block diagram. The functional block diagram shall be as shown in figure 3. 3.5.4 Timing diagram. The timing diagram shall be
19、as shown in figure 4-10. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09627 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Condition
20、s 2/ Limits Unit Min Max DC Specifications High level digital input voltage VIH2 DVDDV Low level digital input voltage VIL0 0.8 High level output drive current IOHST = High VOH= 2.4 V 5 16.3 mA ST = Low VOH= 2.4 V 3 10.3 Low level output drive current IOLST = High VOL= 0.8 V 8 19 ST = Low VOL= 0.8 V
21、 4 11 Hi-Z output leakage current IOZ PD = low or PDO = Low -1 1 A Analog input differential voltage 3/ VID75 1200 mV Analog input common mode voltage 3/ VICAVDD-300 AVDD-37 mV Open circuit analog input voltage VI(OC)AVDD-10 AVDD+10 mV Normal 2-pix/clock power supply current 4/ IDD(2PIX)ODCK = 82.5
22、MHz 2-pix/clock 370 mA Power down current 5/ IPDPD = low 10 mA Output drive power down current 5/ IPDOPDO = Low 35 TYP mA AC Specifications Differential input sensitivity 6/ VID7/ 150 1560 mVp-p Analog input intra pair (+ to -) differential skew 7/ tps0.4 tbit8/ Analog input inter pair or channel to
23、 channel skew 7/ tccs1 tpix9/ Worse case differential input clock jitter tolerance 10/ 7/ 11/ tijit50 ps Fall time of data and control signals 12/ 13/ 11/ tf1ST = Low, CL = 5 pF 2.4 ns ST = High, CL = 10 pF 1.9 Rise time of data and control signals 12/ 13/ 11/ tr1ST = Low, CL = 5 pF 2.4 ST = High, C
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