BS IEC 62528-2007 Standard testability method for embedded core-based integrated circuits《嵌入式基于芯片的集成电路的标准可试性方法》.pdf

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1、BRITISH STANDARDBS IEC 62528:2007Standard Testability Method for Embedded Core-based Integrated CircuitsICS 31.200g49g50g3g38g50g51g60g44g49g42g3g58g44g55g43g50g56g55g3g37g54g44g3g51g40g53g48g44g54g54g44g50g49g3g40g59g38g40g51g55g3g36g54g3g51g40g53g48g44g55g55g40g39g3g37g60g3g38g50g51g60g53g44g42g43

2、g55g3g47g36g58BS IEC 62528:2007This British Standard was published under the authority of the Standards Policy and Strategy Committee on 31 December 2007 BSI 2007ISBN 978 0 580 59318 5National forewordThis British Standard is the UK implementation of IEC 62528:2007.The UK participation in its prepar

3、ation was entrusted to Technical Committee GEL/93, Design automation.A list of organizations represented on this committee can be obtained on request to its secretary.This publication does not purport to include all the necessary provisions of a contract. Users are responsible for its correct applic

4、ation.Compliance with a British Standard cannot confer immunity from legal obligations.Amendments issued since publicationAmd. No. Date CommentsIEC 62528Edition 1.0 2007-11INTERNATIONAL STANDARD Standard Testability Method for Embedded Core-based Integrated Circuits IEEE 1500BS IEC 62528:2007IEE 150

5、0-20051. Overview 61.1 Scope.171.2 Purpose172. Normative references173. Definitions, acronyms, and abbreviations.183.1 Definitions 183.2 Acronyms and abbreviations 134. Structure of this standard 144.1 Specifications144.2 Descriptions . 155. Introduction and motivations of two compliance levels 156.

6、 Overview of the IEEE 1500 scalable hardware architecture . 166.1 Wrapper serial port (WSP) 166.2 Wrapper parallel port (WPP) . 166.3 Wrapper instruction register (WIR). 176.4 Wrapper bypass register (WBY) 176.5 Wrapper boundary register (WBR) 177. WIR instructions 187.1 Introduction 187.2 Response

7、of the wrapper circuitry to instructions . 187.3 Wrapper instruction rules and naming convention 207.4 WS_BYPASS Instruction 217.5 WS_EXTEST instruction 227.6 WP_EXTEST instruction 247.7 Wx_EXTEST instruction. 267.8 WS_SAFE instruction 277.9 WS_PRELOAD instruction. 297.10 WP_PRELOAD instruction. 297

8、.11 WS_CLAMP instruction 317.12 WS_INTEST_RING instruction 337.13 WS_INTEST_SCAN instruction. 347.14 Wx_INTEST instruction 378. Wrapper serial port (WSP) 388.1 WSP terminals . 399. Wrapper parallel port (WPP) . 409.1 WPP terminals . 4010. Wrapper instruction register (WIR). 4010.1 WIR configuration

9、and DR selection. 4010.2 WIR design 4110.3 WIR operation 4411. Wrapper bypass register (WBY) 4711.1 WBY register configuration and selection. 47CONTENTSIEE Introduction . 4BS IEC 62528:2007IEE 1500-2005 2 11.3 WBY operation 4812. Wrapper boundary register (WBR) 4912.1 WBR structure and operation 511

10、2.2 WBR cell structure and operation 5212.3 WBR operation events . 5312.4 WBR operation modes. 5612.5 Parallel access to the WBR 5712.6 WBR cell naming. 6012.7 WBR cell examples . 6112.8 IEEE 1500 WBR example . 6513. Wrapper states 6813.1 Wrapper Disabled and Wrapper Enabled states 6814. WSP timing

11、diagram.6914.1 Specifications. 6914.2 Description. 7014.3 Synchronous reset timing. 7415. WSP configurations for IEEE 1500 system chips . 7515.1 Connecting multiple WSPs 7516. Plug-and-play (PnP). 7816.1 Background and definition. 7816.2 PnP aspects of standard instructions 7916.3 PnP limitations on

12、 protocols 8016.4 Non-PnP in IEEE Std 1500 8017. Compliance definitions common to wrapped and unwrapped cores . 8017.1 General rules 8017.2 Per-terminal rules. 8217.3 Test pattern information rules 8318. Compliance definitions specific to unwrapped cores 8618.1 General rules 8618.2 Per-terminal rule

13、s. 8718.3 Additional test information rules . 8719. Compliance definitions specific to wrapped cores 8819.1 General rules 8819.2 Per-terminal rules. 8919.3 Wrapper protocol information rules 8920. IEEE 1500 application . 9020.1 CTL (IEEE P1450.6) overview . 9020.2 IEEE 1500 examples 91Annex A (norma

14、tive) Bubble diagram definition 107Annex B (informative) WBR cell examples 109Annex C (informative) Relationship of IEEE Std 1500 to IEEE Std 1149.1 11811.2 WBY design 47Annex D (informative) List of participants. 121BS IEC 62528:2007IEE 1500-2005 3 IEEE Std 1500 is a scalable standard architecture

15、for enabling test reuse and integration for embedded coresand associated circuitry. It foregoes addressing analog circuits and focuses on facilitating efficient test ofdigital aspects of systems on chip (SoCs). IEEE Std 1500 has serial and parallel test access mechanisms(TAMs) and a rich set of inst

16、ructions suitable for testing cores, SoC interconnect, and circuitry. In addition,IEEE Std 1500 defines features that enable core isolation and protection. IEEE Std 1500 will reduce test costthrough improved automation, promote good design-for-test (DFT) technique, and improve test qualitythrough im

17、proved access.Core test language (CTL) is the official mechanism for describing IEEE 1500 wrappers and test data associ-ated with cores. CTL is defined in IEEE P1450.6 aand was originally begun as part of the development ofIEEE Std 1500. IEEE Std 1500 was broadly influenced by the past work of the I

18、EEE Std 1149.1 Working Group and hasseveral members from that group. IEEE Std 1149.1 and IEEE Std 1500 have similar goals at different levelsof integration. IEEE Std 1149.1 describes a wrapper architecture and access mechanism designed for thepurpose of testing components of a board whereas IEEE Std

19、 1500 has a similar structure targeted towardstesting cores in an SoC.IEEE Std 1500 has been a continuous effort for its participants due to the goal of resolving the needs of rec-onciling and accommodating disparate test strategies and motives. The greatest effort has been put into sup-porting as m

20、any requirements as possible while still producing a cohesive and consistent standard.Objective of the IEEE 1500 effortThe Embedded Core Test Working Group was approved in 1997 with the charter to develop a standard testmethod for integrated circuits (ICs) containing embedded cores, i.e., reusable m

21、egacells. That method wouldbe independent of the underlying functionality of the IC or its individual embedded cores. The method willcreate the necessary testability requirements for detection and diagnosis of such ICs, while allowing for easeof interoperability of cores originated from distinct sou

22、rces. This method will be usable for all classes of dig-ital cores including hierarchical ones (subclause 15.1 discusses hierarchical core-wrapper configurations).In order to satisfy that charter, the Embedded Core Test Working Group was organized into several taskforces:Core Test LanguageScalable A

23、rchitectureCompliance Definition/Information ModelTerminology/GlossaryEditionMergeable Cores TestBenchmarkingIndustry for output wrapper cells, the cells input, which is connected to a core output. NOTESee CFI pin in Figure 16.3.1.6 cell functional output (CFO): For input wrapper cells, the cells ou

24、tput, which is connected to a coreinput; for output wrapper cells, the cells output, which is connected to a wrapper functional output (WFO). NOTESee CFO pin in Figure 16.3.1.7 cell test input (CTI): A wrapper boundary register (WBR) cells test data input.3.1.8 cell test output (CTO): A wrapper boun

25、dary register (WBR) cells test data output.BS IEC 62528:2007IEE 1500-2005 8 3.1.9 control: The process of applying test pattern stimuli.3.1.10 core: Predesigned circuit block that can be tested as an individual unit.3.1.11 core data register (CDR): Optional data register that belongs to a core being

26、 wrapped.3.1.12 core input: An input terminal of an unwrapped core.3.1.13 core integrator: An entity that incorporates one or more cores into an system on chip (SoC).3.1.14 core isolation: A test mode feature preventing core-to-core or core-to-UDL (i.e., user-defined logic)interaction.3.1.15 core ou

27、tput: An output terminal of an unwrapped core.3.1.16 core provider: An entity that designs cores that can be reused in other designs.3.1.17 core test: A test methodology that is applied to an embedded core.3.1.18 core test language (CTL): A standard language for core suppliers to provide test data t

28、hat can beused to test a core once it is integrated into a system on chip (SoC). The language presents a format todescribe test and support data so that the core can be effectively integrated, reused and tested. NOTESee IEEE P1450.6 reference documentation.3.1.19 dedicated shift path: A shift path c

29、omprising storage elements that do not participate in functionaloperation.3.1.20 dedicated wrapper (cell): A wrapper style that does not share hardware with core functionality. Thisstyle allows certain test operations to occur concurrently and transparently during functional operation.This definitio

30、n could apply to individual cells.3.1.21 external safe state: A configuration of safe state in which the outputs of a core are in a state that pre-vents them from interfering with a block of logic outside the core. See also internal safe state; safe state.3.1.22 firm core: A predesigned block of fun

31、ctional logic such as a macro, megacell, or memory that has aprocess technology-dependent netlist representation and may be amenable to some modification.3.1.23 hard core: A predesigned block of functional logic such as a macro, megacell, or memory that has aphysical implementation that cannot be mo

32、dified.3.1.24 hybrid instruction: A wrapper instruction that has mixed use of wrapper serial port (WSP) andwrapper parallel port (WPP) terminals.3.1.25 input cell: A wrapper boundary register (WBR) cell that is provided on a core input.3.1.26 internal safe state: A configuration of safe state whereb

33、y a core is protected from the impact of a testoutside the core. See also external safe state; safe state.3.1.27 interoperability: See plug-and-play (PnP).3.1.28 inward facing (IF) mode: The test mode where core inputs are controlled by the wrapper boundaryregister (WBR) and core outputs are observe

34、d by the WBR.BS IEC 62528:2007IEE 1500-2005 9 3.1.29 mergeable core: With respect to testability, a core that can be integrated with other cores and user-defined logic (UDL) into a system on chip (SoC) so that a uniform design-for-test (DFT) methodology canbe applied across the entire system. A typi

35、cal mergeable core is provided using a register transfer level(RTL) or gate-level description.3.1.30 merged core: With respect to testability, a core that is integrated with other cores and user-definedlogic (UDL) into a system on chip (SoC) so that a uniform design-for-test (DFT) methodology could

36、beapplied across the entire system.3.1.31 nonmergeable core: With respect to testability, a core that cannot be integrated to apply a uniformdesign-for-test (DFT) methodology to the entire system on chip (SoC). A typical nonmergeable core comeswith a physical design implementation that does not acco

37、mmodate modification of the test methodology. Anonmegeable core may be represented as a block-box design, making standard automatic test pattern gener-ation (ATPG) impossible on such a core.3.1.32 nonmerged core: With respect to testability, a core that has not been integrated with other cores andus

38、er-defined logic (UDL) into a system on chip (SoC) so that a uniform design-for-test (DFT) methodologycould be applied across the entire system.3.1.33 normal mode: The mode in which the wrapper boundary register (WBR) does not interfere with thefunctional operation of a wrapped core. 3.1.34 observat

39、ion: The process of monitoring pattern response.3.1.35 output cell: A wrapper boundary register (WBR) cell that is provided for a core output.3.1.36 outward facing (OF) mode: The test mode where wrapper functional outputs (WFOs) are controlledby the wrapper boundary register (WBR) and wrapper functi

40、onal inputs (WFIs) are observed by the WBR.3.1.37 parallel instruction: A wrapper instruction that uses wrapper parallel port (WPP) terminals and alsoconfigures the wrapper bypass register (WBR) between wrapper serial input (WSI) and wrapper serial out-put (WSO).3.1.38 pattern set: A collection of t

41、est vectors intended for manufacturing test. In the context of core testlanguage (CTL), a pattern set is a collection of pattern constructs and their associated macros and proceduresbrought together with PatternBurst and PatternExecs.3.1.39 plug-and-play (PnP): A minimum level of interoperability be

42、tween various core wrappers in a sys-tem on chip (SoC).3.1.40 safe data: Data that satisfy safe state configuration requirements. These data are user-defined.3.1.41 safe state: A property whereby a test of one block of logic is prevented from interfering with or dam-aging another block of logic. See

43、 also external safe state; internal safe state.3.1.42 selectWIR: The IEEE 1500 wrapper terminal that determines the selection of a wrapper register(WR). A value of 1 represents selection of the wrapper instruction register (WIR), and a value of 0 repre-sents selection of a wrapper data register (WDR

44、).3.1.43 serial instruction: A wrapper instruction that exclusively uses wrapper serial port (WSP) terminals.3.1.44 serial scan chain: The scan chain configuration inside a wrapped core where an internal scan chain isconcatenated with the wrapper boundary register (WBR) chain for the purpose of runn

45、ing the WS_INTEST_SCAN instruction.BS IEC 62528:2007IEE 1500-2005 10 3.1.45 shared wrapper (cell): The wrapper style that shares logic between the test and functional modes ofoperation. Shared cells typically include registered core inputs and outputs that can be used in test mode tocontrol and obse

46、rve core test data. This style prevents simultaneous functional and test operation uses of theshared register.3.1.46 shiftWR: The wrapper terminal used to enable and control a Shift operation in the selected IEEE1500 wrapper register (WR).3.1.47 silent shift path: A wrapper boundary register (WBR) s

47、hift path comprising a dedicated shift pathand implemented to support a Shift operation that keeps wrapper functional output (WFO) terminals static.3.1.48 soft core: A predesigned block of functional logic such as a macro, megacell, or memory with a reg-ister transfer level (RTL) representation. Sof

48、t cores are inherently process technology independent.3.1.49 standard test interface language (STIL): The language in IEEE Std 1450 for representing digitaltest vector data. The core test language (CTL) is an extension of STIL to support a standard way of repre-senting test data for a core.3.1.50 sy

49、stem on chip (SoC): An entire system integrated on a single chip. It may include one or more coreswith user-defined logic (UDL) integrated by the core user or system integrator.3.1.51 test access mechanism (TAM): A feature of a system-on-chip (SoC) design that enables the deliveryof test data to and from cores or core wrappers.3.1.52 test access mechanism (TAM) harness: Wrapper boundary register (WBR) logic that enables thecoupling of a TAM to cell test inputs (CTIs) and cell test outputs (CTOs).3.1.53 test input (TI): The serial test data input of a wrapper bo