BS IEC 62016-2011 Core model of the electronics domain《电子学领域的核心模型》.pdf

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1、raising standards worldwideNO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAWBSI Standards PublicationCore model of theelectronics domainBS IEC 62016:2003BS IEC 62016:200null BRITISH STANDARDNational forewordThis British Standard is the UK implementation onull IEC 62016:200nullnu

2、llThe UK partinullipation in its preparation nullas entrnullsted to Tenullhninullal Committee nullEnullnullnullnullnull Desinulln anulltomationnullA list onull ornullaninullations represented on this nullommittee nullan nulle onulltainedon renullnullest to its senullretarnullnullThis pnullnulllinull

3、ation does not pnullrport to innulllnullde all the nenullessarnull pronullisionsonull a nullontranulltnull Users are responsinullle nullor its nullorrenullt applinullationnullCompliance with a British Standard cannot confer immunity fromlegal obligationsnullISBN nullnullnull 0 nullnull0 nullnull0nul

4、lnull nullICS 2nullnull0null0null01This British Standard nullas pnullnulllished nullnder the anullthoritnull onull the Standards nullolinullnull and Stratenullnull Committee on null1 Anullnullnullst 2011nullnull BSI 2011nullmendments and Corrigenda issued since publicationnullate nullenullt affected

5、 INTERNATIONALSTANDARDIEC62016First edition2003-12Core model of the electronics domainReference numberIEC 62016:2003(E)Publication numberingAs from 1 January 1997 all IEC publications are issued with a designation in the60000 series. For example, IEC 34-1 is now referred to as IEC 60034-1.Consolidat

6、ed editionsThe IEC is now publishing consolidated versions of its publications. For example,edition numbers 1.0, 1.1 and 1.2 refer, respectively, to the base publication, thebase publication incorporating amendment 1 and the base publication incorporatingamendments 1 and 2.Further information on IEC

7、 publicationsThe technical content of IEC publications is kept under constant review by the IEC,thus ensuring that the content reflects current technology. Information relating tothis publication, including its validity, is available in the IEC Catalogue ofpublications (see below) in addition to new

8、 editions, amendments and corrigenda.Information on the subjects under consideration and work in progress undertakenby the technical committee which has prepared this publication, as well as the listof publications issued, is also available from the following: IEC Web Site (www.iec.ch) Catalogue of

9、IEC publicationsThe on-line catalogue on the IEC web site (http:/www.iec.ch/searchpub/cur_fut.htm)enables you to search by a variety of criteria including text searches, technicalcommittees and date of publication. On-line information is also available onrecently issued publications, withdrawn and r

10、eplaced publications, as well ascorrigenda. IEC Just Published This summary of recently issued publications (http:/www.iec.ch/online_news/justpub/jp_entry.htm) is also available by email. Please contact the CustomerService Centre (see below) for further information. Customer Service CentreIf you hav

11、e any questions regarding this publication or need further assistance,please contact the Customer Service Centre:Email: custserviec.chTel: +41 22 919 02 11Fax: +41 22 919 03 00 2 62016 IEC:2003(E) CONTENTS FOREWORD.5 INTRODUCTION.7 1 Scope and object8 2 Reference documents.9 3 General modelling issu

12、es .9 3.1 Ownership and reference 9 3.2 Uniqueness by value .12 3.3 Default values .12 3.4 Optional versus empty sets .12 3.5 Model topology12 4 Concepts13 4.1 The information base.13 4.2 Global ports and global port bundles .13 4.3 Libraries13 4.4 Cells14 4.5 Clusters and cell representation sets.1

13、4 4.6 Cell representations 14 4.7 Master ports and master port bundles .14 4.8 Instances 15 4.9 Instance ports and instance port bundles 15 5 Connectivity .16 5.1 Logical connectivity .16 5.2 Structural connectivity with wide instances 17 5.3 Structural connectivity of connectivity views 19 6 The de

14、sign hierarchy mechanism .21 6.1 The design hierarchy.21 6.2 Annotations .23 7 Core Model for electronic design 24 7.1 Libraries24 7.2 Interfacing to cells .25 7.3 Cell definition hierarchies 27 7.4 Instantiation 27 7.5 Logical connectivity .28 7.6 Structural connectivity .28 7.7 Global connectivity

15、 32 7.8 Design and configuration.33 7.9 Annotation.34 8 Core Model EXPRESS-G34 8.1 Partial EXPRESS-G of cell 35 8.2 Partial EXPRESS-G of cell_representation 36 8.3 Partial EXPRESS-G of cluster .37 8.4 Partial EXPRESS-G of cluster_configuration .38 8.5 Partial EXPRESS-G of cluster_interface39 8.6 Par

16、tial EXPRESS-G of connectivity_generic_bus 40 62016 IEC:2003(E) 3 8.7 Partial EXPRESS-G of connectivity_generic_net .41 8.8 Partial EXPRESS-G of design .42 8.9 Partial EXPRESS-G of global_port 43 8.10 Partial EXPRESS-G of information_base.44 8.11 Partial EXPRESS-G of instance.45 8.12 Partial EXPRESS

17、-G of instance_configuration.46 8.13 Partial EXPRESS-G of library47 8.14 Partial EXPRESS-G of master_port_annotate48 8.15 Partial EXPRESS-G of name_information49 8.16 Partial EXPRESS-G of occurrence_annotate .50 8.17 Partial EXPRESS-G of occurrence_annotate .51 8.18 Partial EXPRESS-G of occurrence_a

18、nnotate .52 8.19 Partial EXPRESS-G of occurrence_hierarchy_annotate.53 8.20 Partial EXPRESS-G of port_structure 54 8.21 Partial EXPRESS-G of property.55 8.22 Partial EXPRESS-G of property_override 56 8.23 Partial EXPRESS-G of signal 57 9 Core Model schemas58 9.1 connectivity_structure_model 58 9.2 c

19、onnectivity_view_model .59 9.3 design_hierarchy_model60 9.4 design_management_model 62 9.5 documentation_model .63 9.6 hierarchy_model64 9.7 information_base_model .67 9.8 library_model 68 9.9 logical_connectivity_model69 9.10 support_definition_model 70 10 Core Model information model72 10.1 connec

20、tivity_structure_model 72 10.2 design_hierarchy_model89 10.3 documentation_model .114 10.4 hierarchy_model116 10.5 information_base_model .157 10.6 support_definition_model 166 11 Index .188 Figure 1 The owner relationship.10 Figure 2 Owner relationship with multiple potential owners 11 Figure 3 The

21、 reference mechanism11 Figure 4 Uniqueness by value12 Figure 5 An example of signal hierarchy 17 Figure 6 A net joins a port on an instance in the commoned style 18 Figure 7 A bus joins a port bundle on an instance in the commoned style 18 Figure 8 A bus joins a port bundle on an instance in the fan

22、ned-out style 19 Figure 9 Internal and external libraries.25 Figure 10 Port bundling 126 4 62016 IEC:2003(E) Figure 11 Port bundling 226 Figure 12 Instantiation .27 Figure 13 Connectivity net .28 Figure 14 Connectivity bus.29 Figure 15 Connectivity bus Commoning 29 Figure 16 Connectivity bus Logical

23、 equivalent of commoning 30 Figure 17 Connectivity bus Fanning-out 30 Figure 18 Connectivity bus Logical equivalent of fanning-out 31 Figure 19 Connectivity bus-slice 31 Figure 20 Connectivity ripper .32 Figure 21 Global port scoping 33 62016 IEC:2003(E) 5 INTERNATIONAL ELECTROTECHNICAL COMMISSION _

24、 CORE MODEL OF THE ELECTRONICS DOMAIN FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international co-operation on all quest

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34、t of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. International Standard IEC 62016 has been prepared by IEC technical committee 93: Design automation. The document was released by the feeder organization, Government Electronics and Information Techn

35、ology Association, a sector of the Electronic Industries Alliance (EIA), for committee draft, comment, and review by members of IEC TC93 1. The text of this standard is based on the following documents: FDIS Report on voting 93/172/FDIS 93/176/RVD Full information on the voting for the approval of t

36、his standard can be found in the report on voting indicated in the above table. _ 1The EIA feeder organization retains the copyright and intellectual property of this work but provides permission for IEC to reproduce and exploit the information contained herein. 6 62016 IEC:2003(E) This standard doe

37、s not follow the rules for the structure of International Standards given in the ISO/IEC Directives, Part 2. The committee has decided that the contents of this publication will remain unchanged until 2012-07. At this date, the publication will be reconfirmed; withdrawn; replaced by a revised editio

38、n, or amended. 62016 IEC:2003(E) 7 INTRODUCTION The Core Model of the electronics domain provides a common basis for design information handled by CAD systems within the electronic domain. It is the purpose of this model to provide a conceptual representation of the electronics domain, so that the c

39、ompliant CAD systems handle a similar set of concepts, thus making inter-communication, sharing and exchange of design information a much easier task. It is not the purpose of this model to describe implementation details or to provide a data representation of electronics domain information. The Cor

40、e Model of the electronics domain, Edition 1.0, is referred to as the “Core Model” throughout this document. The Core Model, in part, has been created by enhancing the industry connectivity consensus model, EDIF CFI DR Alignment Model Version 1.0 (www.edif.org). The chosen description language for t

41、his Core Model is EXPRESS, as defined by ISO 10303-11. It is necessary to describe the Core Model as an information model in order to provide a formal definition of the design information that shall be be recognized by the compliant CAD systems. The benefits of a formal description derive from its a

42、bility to provide an unambiguous representation of concepts, attributes and relationships, and the global rules and constraints that may be applied. By having such a description, it is possible to check the consistency and the correctness of the model as well as to provide a reliable starting-point

43、for further development. It also facilitates the design of correct electronics CAD implementations based on this Core Model, as the actual implementation methods can be checked against the model. This Core Model includes connectivity, hierarchy and design information for the electronics domain. Futu

44、re parts of this Core Model standard may be extended to include other categories of information (for example, cell_representation, schematic representation, the PCB domain, symbols and display information). In order to facilitate the creation of other parts of this Core Model standard, some objects

45、have been used in this Core Model to facilitate support for other parts of the electronics domain. There are two types of such objects. Entities, such as cell_representation, are important concepts that provide support for defining other Core Model parts. Constraints: Some of constraints of this Cor

46、e Model use conditions that are always true. They have been written in this way in order to ensure that they remain valid when the model is extended. 8 62016 IEC:2003(E) CORE MODEL OF THE ELECTRONICS DOMAIN 1 Scope and object This International Standard provides the semantics definitions for the fol

47、lowing categories of information related to electronic circuit designs. Each category of design information is modelled as an EXPRESS schema. The Core Model consists of 10 schemas. Each of them is presented in this document as a separate chapter. At the beginning of each chapter, a description of th

48、e corresponding schema is provided. The hierarchy_model schema describes the hierarchical information of a cell, i.e. the way a cell may be divided into other cells. A circuit may be divided into cells which, in turn, may be further subdivided into other cells, thus creating a hierarchy. The hierarc

49、hy information describes the cells, the possible cell representations and their instances. The design_hierarchy_model schema describes the annotation on an occurrence hierarchy. The definition of a design requires that specific representations (views) of design objects in the hierarchy are selected. This unambiguously creates a configured design hierarchy. This concept is similar to the configuration of a design in VHDL and is related to view selection mech