BS EN 61188-5-8-2008 Printed boards and nprinted board nassemblies — Design nand use — nPart 5-8 Attachment (land joint) nconsiderations — Area array ncomponents (BGA FBGA CGA LGA).pdf

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1、BRITISH STANDARDBS EN 61188-5-8:2008Printed boards and printed board assemblies Design and use Part 5-8: Attachment (land/joint) considerations Area array components (BGA, FBGA, CGA, LGA)ICS 31.180g49g50g3g38g50g51g60g44g49g42g3g58g44g55g43g50g56g55g3g37g54g44g3g51g40g53g48g44g54g54g44g50g49g3g40g59

2、g38g40g51g55g3g36g54g3g51g40g53g48g44g55g55g40g39g3g37g60g3g38g50g51g60g53g44g42g43g55g3g47g36g58BS EN 61188-5-8:2008This British Standard was published under the authority of the Standards Policy and Strategy Committee on 30 May 2008 BSI 2008ISBN 978 0 580 59958 3National forewordThis British Stand

3、ard is the UK implementation of EN 61188-5-8:2008. It is identical to IEC 61188-5-8:2007.The UK participation in its preparation was entrusted to Technical Committee EPL/501, Electronic assembly technology.A list of organizations represented on this committee can be obtained on request to its secret

4、ary.This publication does not purport to include all the necessary provisions of a contract. Users are responsible for its correct application.Compliance with a British Standard cannot confer immunity from legal obligations.Amendments/corrigenda issued since publicationDate CommentsEUROPEAN STANDARD

5、 EN 61188-5-8 NORME EUROPENNE EUROPISCHE NORM March 2008 CENELEC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung Central Secretariat: rue de Stassart 35, B - 1050 Brussels 2008 CENELEC - All righ

6、ts of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. No. EN 61188-5-8:2008 E ICS 31.180 English version Printed boards and printed board assemblies - Design and use - Part 5-8: Attachment (land/joint) considerations - Area array components (BGA, FBGA, CGA, LGA

7、) (IEC 61188-5-8:2007) Cartes imprimes et cartes imprimes quipes - Conception et utilisation - Partie 5-8: Considrations sur les liaisons pistes-soudures - Composants matriciels (BGA, FBGA, CGA, LGA) (CEI 61188-5-8:2007) Leiterplatten und Flachbaugruppen - Konstruktion und Anwendung - Teil 5-8: Betr

8、achtungen zur Montage (Anschlussflche/Verbindung) - Flchenmatrix-Bauelemente (BGA, FBGA, CGA, LGA) (IEC 61188-5-8:2007) This European Standard was approved by CENELEC on 2008-02-01. CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for givin

9、g this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the Central Secretariat or to any CENELEC member. This European Standard exists in three official ve

10、rsions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same status as the official versions. CENELEC members are the national electrotechnical committees

11、of Austria, Belgium, Bulgaria, Cyprus, the Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland and the United Kin

12、gdom. Foreword The text of document 91/705/FDIS, future edition 1 of IEC 61188-5-8, prepared by IEC TC 91, Electronics assembly technology, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 61188-5-8 on 2008-02-01. This European Standard is to be read in conjunction wi

13、th EN 61188-5-1. The following dates were fixed: latest date by which the EN has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2008-11-01 latest date by which the national standards conflicting with the EN have to be withdrawn (dow) 2011

14、-02-01 Annex ZA has been added by CENELEC. _ Endorsement notice The text of the International Standard IEC 61188-5-8:2007 was approved by CENELEC as a European Standard without any modification. _ BS EN 61188-5-8:2008 2 CONTENTS 0INTRODUCTION.1H1H5 1 Scope.2H2H6 2 Normative references .3H3H6 3 Gener

15、al information 474H 7 3.1 General component description .5H5H7 3.2 Marking .6H6H7 3.3 Carrier packaging format . 787H 8 3.4 Process considerations .8H8H8 4 BGA (square) .9H9H8 4.1 Field of application 10H10H8 4.2 Component descriptions 11H11H8 4.2.1 Basic construction . 18H12H 8 4.2.2 Termination ma

16、terials 913H13H 4.2.3 Marking . 14H14H10 4.2.4 Carrier package format 15H15H10 4.2.5 Process considerations 16H16H10 4.3 Component dimensions (square) . 17H17H10 4.3.1 PBGA 1,5 mm pitch component dimensions (square). 18H18H11 4.3.2 PBGA 1,27 mm pitch component dimensions (square). 19H19H13 4.3.3 PBG

17、A 1,00 mm pitch component dimensions (square). 20H20H14 4.4 Solder joint fillet design . 21H21H16 4.4.1 Solder joint fillet design Non-collapsing, collapsing (level 3) . 22H22H16 4.5 Land pattern dimensions . 23H23H17 4.5.1 PBGA 1,5 mm pitch land pattern dimensions (square) . 24H24H18 4.5.2 PBGA 1,2

18、7 mm pitch land pattern dimensions (square) . 25H25H20 4.5.3 PBGA 1,00 mm pitch land pattern dimensions (square) . 26H26H22 5 FBGA (square) . 27H27H24 6 BGA (rectangular) 28H28H24 6.1 Field of application 29H29H24 6.2 Component descriptions 30H30H24 6.2.1 Basic construction . 31H31H24 6.2.2 Terminat

19、ion materials 32H32H24 6.2.3 Marking . 33H33H25 6.2.4 Carrier package format 34H34H25 6.2.5 Process considerations 35H35H25 6.3 Component dimensions (rectangular) 36H36H25 6.4 Solder joint fillet design . 37H37H26 6.4.1 Solder joint fillet design Collapsing (level 3) . 38H38H26 6.4.2 Land approximat

20、ion . 39H39H27 6.4.3 Total variation . 40H40H27 6.5 Land pattern dimensions . 41H41H27 7 FBGA (rectangular) 42H42H28 8 CGA . 43H43H28 9 LGA 44H44H28 BS EN 61188-5-8:2008 3 Bibliography 45H45H29 Figure 1 Area array land pattern configuration .46H46H6 Figure 2 BGA physical configuration examples 947HF

21、igure 3 High land and eutectic solder ball and joint comparison .948H48HFigure 4 BGA (square). 49H49H10 Figure 5 General BGA dimensional characteristics. 50H50H11 Figure 6 Solder joint fillet design 51H51H17 Figure 7 BGA (square) land pattern dimensions. 52H52H18 Table 1 Ball diameter sizes53H53H7 T

22、able 2 BGA products with pitch of 1,5 mm 54H54H12 Table 3 BGA products with pitch of 1,27 mm 55H55H13 Table 4 BGA products with pitch of 1,0 mm 56H56H15 Table 5 BGA product land patterns with pitch of 1,50 mm 57H57H19 Table 6 BGA product land patterns with pitch of 1,27 mm 58H58H21 Table 7 BGA produ

23、ct land patterns with pitch of 1,00 mm 59H59H23 Table 8 Rectangular BGA products with pitch of 1,27 mm 60H60H26 Table 9 Rectangular BGA product land patterns with pitch of 1,27 mm. 61H61H28 BS EN 61188-5-8:2008Annex ZA (normative) Normative references to international publications with theircorrespo

24、nding European publications.30 4 INTRODUCTION This part of IEC 61188 covers land patterns for area array components which include ball grid array (BGA) parts (rigid, flexible or ceramic substrate); fine pitch ball grid array (FBGA) parts (rigid or flexible substrate); column grid array (CGA) parts (

25、ceramic substrates) and land grid array (LGA) parts (ceramic substrates). Each clause contains information in accordance with the area array family of components and their requirements for appropriate land patterns. The proposed land pattern dimensions in this standard are based upon the fundamental

26、 tolerance calculation combined with the given land geometries and courtyard excesses (see IEC 61188-5-1, Generic requirements). The courtyard includes all issues of the normal manufacturing necessities. The unaltered land pattern dimensions of this part are generally applicable for the solder paste

27、 application plus the reflow soldering process. Although other standards in the IEC 61188-5 series define three levels of land pattern dimensioning, this standard will only define two levels. One level (level 2) is for non collapsing BGA balls; the other level (level 3) is for those BGA components w

28、here the ball does collapse around the land. All land descriptions are non-solder mask defined. Each land pattern has been assigned an identification number to indicate the characteristics of the specific robustness of the land patterns. Users also have the opportunity to organize the information so

29、 that it is most useful for their particular design. If a user has good reason to use a concept different from that of IEC 61188-5-1, or if the user prefers unusual land geometries, this standard should be used for checking the resulting ball to land relationship. It is the responsibility of the use

30、r to verify the SMD land patterns used for achieving an undisturbed mounting process including testing and an ensured reliability for the product stress conditions in use. In addition, the size and shape of the proposed land pattern may vary according to the solder resist aperture, the size of the l

31、and pattern extension (dog bone), the via within the extension, or if the via is in the land pattern itself. Dimensions of the components listed in this standard are of those available in the market, and regarded as reference only. BS EN 61188-5-8:2008 5 PRINTED BOARDS AND PRINTED BOARD ASSEMBLIES D

32、ESIGN AND USE Part 5-8: Attachment (land/joint) considerations Area array components (BGA, FBGA, CGA, LGA) 1 Scope This part of IEC 61188 provides information on land pattern geometries used for the surface attachment of electronic components with area array terminations in the form of solder balls,

33、 solder columns or protective coated lands. The intent of the information presented herein is to provide the appropriate size, shape and tolerances of surface mount land patterns to ensure sufficient area for the appropriate solder joint, and also allow for inspection, testing and reworking of those

34、 solder joints. Each clause contains a specific set of criteria such that the information presented is consistent, providing information on the component, the component dimensions, the solder joint design and the land pattern dimensions. The land pattern dimensions are based on a mathematical model

35、that establishes a platform for a solder joint attachment to the printed board. The existing models create a platform that is capable of establishing a reliable solder joint no matter which solder alloy is used to make that joint (lead-free, tin lead, etc.). Process requirements for solder reflow ar

36、e different depending on the solder alloy and should be analyzed so that the process is taking place above the liquidus temperature of the alloy, and remains above that temperature a sufficient time to form a reliable metallurgical bond. Area array land patterns do not use “land protrusion“ concepts

37、 and attempt to match the characteristics of the physical and dimensional termination properties. There are several configurations available, as shown in Figure 1. However, the tables provided show only the optimum dimension across the outer construction of the land. Circle Hexagon Via in Pad Dog Bo

38、ne IEC 2028/07 Figure 1 Area array land pattern configuration 2 Normative references The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document

39、(including any amendments) applies. BS EN 61188-5-8:2008 6 IEC 60068-2-58, Environmental testing Part 2-58: Tests: Test Td Test methods for solderability, resistance to dissolution of metallization and to soldering heat of surface mounting devices (SMD) IEC 60191-2 (all parts), Mechanical standardiz

40、ation of semiconductor devices Part 2: Dimensions IEC 61188-5-1, Printed boards and printed board assemblies Design and use Part 5-1: Attachment (land/joint) considerations Generic requirements IEC 62090, Product package labels for electronic components using bar code and two-dimensional symbologies

41、 3 General information 3.1 General component description The area array family is characterized by terminations that are on a particular pitch and contain a number of rows and columns for the total IO termination pin count. The BGA family uses a solder ball as a termination and may have a square or

42、rectangular package configuration. The family includes both moulded plastic and ceramic case styles. The acronyms PBGA (plastic ball grid array), CBGA (ceramic ball grid array), FBGA (fine pitch ball grid array), and TBGA (tape ball grid array) are also used to describe the family since they all use

43、 a ball termination in an array format. Other enhancements such as the addition of thermal heat distributors may be included in any of the package types described. There are several ball pitch variations within the family; these range from 1,50 mm to 0,25 mm as shown in Table 1. The lower pitch item

44、s (below 0,40 mm) are predicted for future component configurations. Table 1 Ball diameter sizes Pitch mm Solder bump nominal diameter mm Solder bump diameter variation mm 1,50; 1,27 0,75 0,90 0,65 1,00 0,60 0,70 0,50 1,00; 0,80 0,50 0,55 0,45 1,00; 0,80; 0,75 0,45 0,50 0,40 0,80; 0,75; 0.65 0,40 0,

45、45 0,35 0,80; 0,75; 0,65; 0,50 0,30 0,35 0,25 0,40 0,25 0,28 0,22 0,30 0,20 0,22 0,18 0,25 15 0,17 0,13 3.2 Marking The area array family of parts are generally marked with the manufacturers part numbers, manufacturers name or symbol and a pin 1 indicator. Some parts may have a pin 1 feature in the

46、case shape instead of a pin 1 marking. Additional markings may include date-code manufacturing lot and/or manufacturing location. Bar code marking should be in accordance with IEC 62090. BS EN 61188-5-8:2008 7 3.3 Carrier packaging format Carrier tray packaging format or tape and reel may be provide

47、d. Either format is acceptable and is usually specified by the component manufacturer or the assembler. Choice of format is usually dependent on size of component and volume to be assembled. Bulk packaging is not acceptable because of termination coplanarity issues and the requirements for placement

48、 and soldering. 3.4 Process considerations Area array packages are normally processed by reflow solder operations. There is also a process difference between the solder application for those terminations that collapse slightly during soldering as defined in level 3 of this standard, and those termin

49、ations that do not collapse (level 2) where a significant amount of additional solder paste is required. In conjunction with the right land size, the volume of the solder paste application is a fundamental parameter to keep under control in order to have a good reflow quality yield and reliable solder joint. Paste volume deposition may be a matter of SPC adoption at the print process step. Fine pitch ball parts may require special processing outside the normal pic