BS CECC 90115-1994 Specification for harmonized system of quality assessment for electronic components - Blank detail specification digital gate array integrated circuits《电子元器件用质量评.pdf

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1、BRITISH STANDARD BS CECC 90115:1994 Specification for Harmonized system ofquality assessment for electronic components Blankdetail specification Digital gate array integrated circuitsBSCECC90115:1994 BSI 02-2000 ISBN 0 580 34520 3 Amendments issued since publication Amd. No. Date CommentsBSCECC90115

2、:1994 BSI 02-2000 i Contents Page National foreword ii Foreword iii Text of CECC90115 1BSCECC90115:1994 ii BSI 02-2000 National foreword This BritishStandard has been prepared under the direction of the Electronic Components Standards Policy Committee (ECL/-). It is identical with CECC90115:1993 Har

3、monized system of quality assessment for electronic components. Blank detail specification: Digital gate array integrated circuits published by the European Committee for Electrotechnical Standardization (CENELEC) Electronic Components Committee (CECC). CECC90115 was prepared by CECC WG9 Semiconduct

4、or integrated circuits and the UnitedKingdom participation in the drafting was provided by Technical Committee ECL/24, Semiconductors. Scope. The standard is related to non-finished products, where the customer is involved in their design, layout and specification. As a consequence, this standard de

5、scribes requirements for “tools” (e.g.for design, verification test, and measurement), rather than requirements for components. The application of this specification requires that the relevant process technology and the associated manufacturing line are already qualified. Textual errors. When adopti

6、ng the text of the International Standard, the textual errors listed below were discovered. In the last line of the table in2.2, “capacitives” should read “capacitive”. In the second paragraph of4.3, “caracteristics” should read “characteristics”. The BritishStandard which implements the CECC Rules

7、of Procedure is BS9000-2:1991 General requirements for a system for electronic components of assessed quality Part2: Specification for the national implementation of the CECC system. Detail specification. Detail specification shall comply with the requirements ofthis Blank Detail Specification and B

8、S CECC00111-4:1991 Rules of Procedure11. Specifications. Part4: Regulations for CECC detail specification. A British Standard does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their correct application. Compliance with a British St

9、andard does not of itself confer immunity from legal obligations. Cross-references International Standard Corresponding BritishStandard CECC90000 BS CECC90000:1991 Harmonized system of quality assessment for electronic components. Generic specification: Monolithic integrated circuits Identical CECC9

10、0100 BS EN90100:1993 Harmonized system of quality assessment for electronic components. Sectional specification: Digital monolithic integrated circuits Identical IEC747-1 BS6493 Semiconductor devices Part1 Discrete devices Section1.1:1984 General Identical IEC748 Part2 Integrated circuits All Parts

11、are identical Summary of pages This document comprises a front cover, an inside front cover, pagesi andii, theCECC title page, pages ii to iv, pages1 to6 and a back cover. This standard has been updated (see copyright date) and may have had amendments incorporated. This will be indicated in the amen

12、dment table on the inside front cover.BS CECC90115:1994 ii BSI 02-2000 Contents Page Foreword iii 1 General description 3 1.1 Definition 3 1.2 Technology 3 2 General description of the arrays and test vehicle 3 2.1 Description of family, arrays, and/or demonstrators 3 2.2 Library description rules 4

13、 2.3 Test vehicles (LTV) 5 2.3.1 General description 5 2.3.2 LTV types 5 2.3.3 Electrical characteristics of the LTV 5 3 Simulation tools 5 4 Quality assessment procedures 6 4.1 General Procedures 6 4.1.1 Qualification of the technology 6 4.1.2 Lot by lot tests 6 4.2 Cell library qualification 6 4.2

14、.1 Design of cells/macros 6 4.2.2 Qualification of cells or macros 6 4.3 Design tool qualification 6 4.4 Customized devices qualification 6BS CECC90115:1994 BSI 02-2000 iii Foreword The CENELEC Electronic Components Committee (CECC) is composed of thosemember countries of the European Committee for

15、Electrotechnical Standardization (CENELEC) who wish to take part in a harmonized System for electronic components of assessed quality. The object of the System is to facilitate international trade by the harmonization of the specifications and quality assessment procedures for electronic components,

16、 and by the grant of an internationally recognized Mark, or Certificate, of Conformity. The components produced under the System are thereby acceptable in all member countries without further testing. This specification has been formally approved by the CECC, and has been prepared for those countrie

17、s taking part in the System who wish to issue national harmonized specifications for DIGITAL GATE ARRAY INTEGRATED CIRCUITS. It should be read in conjunction with the current regulations for theCECC System. At the date of printing of this specification, the member countries of the CECC are Austria,

18、Belgium, Denmark, Finland, France, Germany, Ireland, Italy, theNetherlands, Norway, Portugal, Spain, Sweden, Switzerland and theUnitedKingdom, and copies of it can be obtained from the addresses shown on the blue fly sheet. Preface This blank detail specification (BDS) was prepared byCECCWG9:“INTEGR

19、ATED CIRCUITS”. It is based, wherever possible, on the Publications of the International Electrotechnical Commission and in particular on IEC747: Semiconductor devices Discrete devices and integrated circuits, and IEC748: Semiconductor devices Integrated circuits. The text of this specification was

20、circulated to the CECC for voting in the documents listed below and was approved for publication: It is recognized that the layout proposed cannot be applied to all detail specifications based on this document. For instance, it may be preferable to indicate the limiting values in the form of a table

21、 when several similar devices appear in the same detail specification. AVIS In accordance with the decision of the CECC Management Committee, this specification is published initially in English and French. The German text will follow as soon as it has been prepared. Document Date of Voting Report o

22、n the Voting CECC(Secretariat)2648 January1991 CECC(Secretariat)2788iv blankBS CECC90115:1994 BSI 02-2000 1 General This document represents a new concept for BDSs, different from the other BDSs published by WorkingGroup9. This is necessary, because it is related to non-finished products, where the

23、customer is involved in their design, layout and specification. As a consequence, this BDS describes requirements for “tools” (e.g.fordesign, verification, test, and measurement), rather than requirements for components. The application of this specification requires that the relevant process techno

24、logy and the associated manufacturing line are already qualified. The following information is given for guidance. Scope This BDS relates to Integrated Gate Arrays in accordance with IEC748: Semiconductor devices Integrated circuits. A gate array is a circuit having a design methodology based on a t

25、echnological process and function library which elements have been prediffused. The set of such gate arrays shall be defined in terms of complexity: maximum number of equivalent gates maximum percentage of usable gates (where appropriate) die size I/O number. Related documents See2.1 of CECC90100 an

26、d2.2 of CECC90000. Structure of Detail Specifications Clause numbering of DSs shall be in accordance with that of this document. Units, symbols and terminology See2.3 of CECC90100 and2.3 of CECC90000. Application of Quality Assessment Procedures See3 of CECC90100 and CECC90000.BS CECC90115:1994 2 BS

27、I 02-2000 Layout of front page of detail specificationBS CECC90115:1994 BSI 02-2000 3 1 General description 1.1 Definition TTV: Technology Test Vehicle: (see CQC of ASF) LTV: Library Test Vehicle: the content and use of this vehicle are described in2.3. LTVs are intended for qualification of library

28、 cells and design tools. CD: Demonstrator IC: a circuit implemented with the gate array. The functions of this circuit are to be defined by the IC manufacturer. It is intended for performance evaluation by users. CC: Customer circuit: a circuit based on the gate array to implement customer circuits.

29、 1.2 Technology The technology employed shall either be defined in a Detail Specification (DS), or, where there is no suitable DS, by means of a concise description. 2 General description of the arrays and test vehicle 2.1 Description of family, arrays, and/or demonstrators The following shall be sp

30、ecified: power supplies and limiting conditions number of physical gates or cells number of usable gates or cells maximum dynamic power dissipation for the device and per MHz or per functional unit number of available buffers per output percentage or number of I/O buffers usable as output number of

31、outputs which can be simultaneously switched under specified conditions (supply voltage, loading, etc.) for each array of a family: 1) physical layout information including (where appropriate). identification and position of power supply and ground pads identification and position of special pads (o

32、scillators, test pads, etc.) position of the I/O stages locations of active, and interconnection, zones description of interconnection capability (number of levels, horizontal and vertical grids routing over active areas, etc.) 2) locations of bus or other techniques for supply distribution and proh

33、ibited regions 3) die size(s) 4) packaging availability 5) functional description of the test vehicle of customer circuits 6) static characteristics: see library 7) dynamic characteristics: see library and simulation.BS CECC90115:1994 4 BSI 02-2000 2.2 Library description rules The parameters listed

34、 below shall be specified. General Library For all cells maximum acceptable load t PLH , t PHL worst/best cases of temperature, power supply and technology for a specified fan out and capacitive load or(2) typical values for stated conditions of temperature, power supply, fan out and capacitive load

35、 variation of t PLHand t PHLin terms of: loading conditions (also capacitive) temperature(3) supply voltage(3) process(3) interconnections name of the function reference of the function logical or analogical symbol of the function truth table and/or sequencial diagram number of gates number of eleme

36、ntary cells electrical diagram symbolic topology pin assignment fan in and fan out timing diagrams symbolic description simulation model internal equivalent capacitance C PD For I/O cells only V OH /V OL protection level (ESD, latch-up.)(4) number of used pads acceptable capacitives loads X X(1) X X

37、 X X X X X X X X X X X X X X(1) X(1) X X X(1) X(1) X(1) X(1) X X (1) Optional. (2) At the manufacturers option. (3) Optional except for the typical t PLH , t PHLdescription. (4) ESD: as in Publication IEC747-1 chapter9. Latch-up: as in IEC47A (Central Office)252 and266.BS CECC90115:1994 BSI 02-2000

38、5 2.3 Test vehicles (LTV) 2.3.1 General description The LTV described in this document shall be designed and manufactured in accordance with claimed capability (technology, configuration) and shall allow verification of: interconnection characteristics: 1) line delay (per unit length) where characte

39、ristics are given as minimum and maximum based onsimulations 2) if applicable, electrical input parameters for simulation to allow calculation of line delays per unit length (such as simulator input parameters, or library elements such as polysilicon resistors, metallization, etc.) noise immunity: 1

40、) crosstalk, where appropriate 2) static parameters: V IL , V IH , V OL , V OH intrinsic speed of the technology: The maximum switching speed(s) or frequencies obtainable with one or more of the library elements (such as a ring oscillator, or two stage divider). loading effects on internal cells or

41、macros (circuits) Where loading effects have not been taken into account in the verification of separately accessible functions, then a specific test shall be performed: buffers shall: 1) be documented (characteristics simulation results) 2) allow evaluation of their behaviour in respect of influenc

42、es such as: perturbations: crosstalk on non-active outputs interface: power supply network power consumption. 2.3.2 LTV types LTV shall contain a range of cells/macros which is representative of the claimed capability subjected to the satisfaction of the ONS. The cells shall be described in terms of

43、 basic functions and shall demonstrate the complexity of functions available for design. At the discretion of the manufacturer these may be implemented on one or more different test vehicles. With the agreement of the ONS, alternative cells or macros of equivalent complexity may be provided. 2.3.3 E

44、lectrical characteristics of the LTV Power supply consumption shall be defined: in static mode in dynamic mode: measured in mA/MHz/gate. The test configurations shall be specified by the manufacturer. 3 Simulation tools A concise description of, or reference to, the simulation tool(s) shall be given

45、.BS CECC90115:1994 6 BSI 02-2000 4 Quality assessment procedures 4.1 General Procedures 4.1.1 Qualification of the technology Qualification and maintenance of the technology shall be in accordance with the Procedures for Capability Approval given in the Generic Specification. The Technology Test Veh

46、icles (TTVs) submitted for assessment shall be representative of the manufacturing line employed for customized devices and the limits of technology. This requirement includes all relevant operations, including those for circuit customization, assembly, and finishing operations. 4.1.2 Lot by lot tes

47、ts Lot by lot tests shall be performed in accordance with the requirements of the applicable quality assessment level. Group A tests shall be performed on each customer device according to the relevant detail specification. The Detail Specification agreed between the manufacturer and the customer sh

48、all contain the specific elements of the function as defined by the customer, i.e.electrical characteristics (static and dynamic), and test patterns. 4.2 Cell library qualification Stability of the technology is assessed by the Capability Approval Procedures: Qualification of the cells or macros is

49、therefore limited to their function(s). 4.2.1 Design of cells/macros Each cell or macro shall be designed according to the design rules defined by the manufacturer. These rules may be disclosed to the customer for their own design. Validation of these requirements shall be performed by means of audits conducted by the ONS, who may be assisted by selected experts who shall be agreed by the manufacturer. 4.2.2 Qualification of cells or macros Tes