JEDEC JESD73-1-2001 Standard for Description of 3 3 V NFET Bus Switch Devices《3 3V NFET公共汽车开关设备的描述标准》.pdf

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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD73-1AUGUST 2001JEDECSTANDARDStandard for Description of 3.3 V NFET Bus Switch DevicesNOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approvedthrough the JEDEC Council level and subsequently reviewed and approve

2、d by the EIA General Counsel.JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purchaser in selecting and obtaining with m

3、inimum delay theproper product for use by those other than JEDEC members, whether the standard is to be used eitherdomestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoption mayinvolve patents or articles, materials, or processes. By

4、such action JEDEC does not assume any liability toany patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards orpublications.The information included in JEDEC standards and publications represents a sound approach to productspecification and application, prin

5、cipally from the solid state device manufacturer viewpoint. Within theJEDEC organization there are procedures whereby a JEDEC standard or publication may be furtherprocessed and ultimately become an EIA standard.No claims to be in conformance with this standard may be made unless all requirements st

6、ated in thestandard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication shouldbe addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA22201-3834, (703)907-7559 or www.jedec.org.Published byJEDEC Solid State

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10、7559 JEDEC Standard No. 73-1Page 1STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES(From Board Ballot JCB-00-98, formulated under the cognizance of the JC-40 Committee on Digal Logic.)1 ScopeThis standard covers specifications for a family of 3.3 V NMOS FET bus switch devices. Not included i

11、n this document are device specific parameters and performance levels that the vendor must also supply for full device description. The purpose of this document is to provide a set of uniform data sheet parameters for the description of bus switch devices. This standard includes required parameters,

12、 test con-ditions, test levels, and measurement methods for data sheet descriptions of bus switch devices.2 Definitions for the purpose of this documentswitch device: A semiconductor logic device designed to connect or disconnect busses or control signals without active drivers in the connection pat

13、h.connect: A state in a switch device characterized by a minimum series impedance through the designated electrical path.disconnect: A state in a switch device characterized by the high series impedance of the designated electrical path.JEDEC Standard No. 73-1Page 23 Standard specifications3.1 Absol

14、ute maximum continuous ratings 1,2NOTE 1 Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated cond

15、i-tions is not implied.NOTE 2 Under transient conditions these ratings may be exceeded as defined elsewhere in this specification.NOTE 3 The dc negative voltage ratings may be exceeded if the dc input clamp current ratings are observed. 3.2 Recommended operating conditions3.3 Capacitance(1)NOTE 1 Ca

16、pacitance is characterized but not testedSymbol Parameter Rating UnitsVDDSupply voltage -0.5 to 4.6 VVI dc input voltage, control terminals(3)-0.5 to 4.6 VVSW dc switch voltage(3)-0.5 to 4.6 VIIKdc input clamp -50 mAIOKdc clamp current, switch terminals -50 mAISWdc continuous channel current 120 mAT

17、STGStorage temperature -65 to 150 CSymbol Parameter Min Max UnitVDDSupply voltage 3.0 3.6 VVINControl input voltage 0 3.6 VVSWSwitch terminal voltage 0 3.6 VTAOperating free-air temperature -40 85CSymbol Parameter Condition Typ. UnitCINControl input capacitance pFCSWSwitch terminal capacitance Switc

18、h disconnected pFJEDEC Standard No. 73-1Page 33 Standard specifications (contd)3.4 Power supply characteristicsNOTE 1 Per TTL driven control inputNOTE 2 All switch inputs grounded. One control pin toggling. All other control pins at VDDor GND.3.5 Switching characteristics over operating rangeNOTE 1

19、Path must be specified.NOTE 2 This parameter is not tested.Symbol Description Test Conditions Max UnitIDDQuiescent power supply current VDD= 3.6 VVSW= GND or VDDmAIDDQuiescent power supply currentTTL control inputs high(1)VDD= 3.6 VVIN= 2.0 VVSW= GNDAQD Dynamic power supply current(2)VSW= GNDControl

20、 pin toggling at 10 MHz and 50% duty cycleA/MHzSymbol Description Min Typ Max UnittPLHtPHLData path propagation delay(1,2)nstPZHtPZLSwitch connect delay(1)nstPHZtPLZSwitch disconnect delay(1)nsJEDEC Standard No. 73-1Page 43 Standard specifications (contd)3.6 DC specificationsNOTE 1 See the manufactu

21、rers data sheet. NOTE 2 The connect path must be specified. NOTE 3 Resistance is measured as V/I. For VSW= 0 V, the resistance is measured while VOUTis pulled higher to the designated current level. For VSW= 2.4 V, the resistance is mea-sured while VOUTis pulled lower to the designated current level

22、.NOTE 4 Not more than one output should be tested at a time. Duration of the test must not exceed one second. This is an optional parameter.NOTE 5 Optional specification for voltage translation. VDD= the recommended voltage for 3.3 V to 2.5 V voltage translation. This parameter is characterized but

23、not tested.NOTE 6 This is an optional parameter.Symbol Parameter Test Conditions Min Max UnitVIHHigh-level input voltage 2.0VVILLow-level input voltage0.8 VVPASSPass voltage drop (VDD VO)VSW= VDDVDD = Note 5Iout = -100 AVRON Switch connect resistance(2,3)VSW= 0 V ISW= (1)VSW=2.4 V ISW= (1)IOS Short

24、circuit current(2,4)VSW= VDDVOUT= GNDmAIDDQuiescent power supply current VDD= Max., VIN= VDDor GNDAVIKClamp diode voltage Switch TerminalsISW= -18 mAVControl Terminals,IIN= -18 mAVIOZCurrent during switch disconnect VDD= Max.VSW= GND to 3.6 VVOUT= GNDAIILIIHControl input current VDD= Max. VI= GNDVI=

25、 VDDAIOFF Switch terminal leakage(6)VDD= 0 VVSW= 3.6 VJEDEC Standard No. 73-1Page 54 Test circuits and switching waveformsCL= 50 pF or equivalent (includes test setup and probe capacitance).RL= R1= 500 or equivalentRT= Pulse generator termination resistance Pulse generator has the following characte

26、ristics: tr 2.5 ns, tf= 2.5 ns, PRR 10 MHz4.1 Propagation delay measurementsTest Switch S1tPLHOpentPHLOpentPZHOpentPZL6.0 VtPHZOpentPLZ6.0 VDUTPulseGeneratorRTCLR1RL6.0 VOpenGNDSwitch InputSwitch OutputtPLHtPHL3.0 V1.5 V0 VVOHVOL1.5 VJEDEC Standard No. 73-1Page 64 Test circuits and switching wavefor

27、ms (contd)4.2 Connect delay measurements4.3 Disconnect delay measurementsNOTE Reference to Other Applicable JEDEC Standards and PublicationsControl InputSwitch OutputtPZHtPZL3.0 V1.5 V0 VVOHVOL1.5 VSwitch OutputVOHVOL1.5 V(Switch Input = GND)(Switch Input = 3.0 V)Control InputSwitch OutputtPLZtPHZ3.0 V1.5 V0 VVOHVOLSwitch OutputVOHVOL(Switch Input = GND)(Switch Input = 3.0 V)VOL + 0.3 VVOH - 0.3 V