JEDEC JESD51-6-1999 Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)《集成电路热测试方法环境条件 强制对流(流动空气)》.pdf
《JEDEC JESD51-6-1999 Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)《集成电路热测试方法环境条件 强制对流(流动空气)》.pdf》由会员分享,可在线阅读,更多相关《JEDEC JESD51-6-1999 Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)《集成电路热测试方法环境条件 强制对流(流动空气)》.pdf(20页珍藏版)》请在麦多课文档分享上搜索。
1、EIA/ JEDEC STANDARD Integrated Circuit Thermal Test Method Environmental Conditions = Forced Convection (Moving Air) JESD51-6 MARCH 1999 ELECTRONIC INDUSTRIES ALLIANCE JEDEC Solid State Technology Association Electronic Industries Alliance NOTICE EWJEDEC standards and publications contain material t
2、hat has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the ELA General Counsel. EWJEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and pur
3、chasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. EWJEDEC standards a
4、nd publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the EWJEDEC standards or public
5、ations. The information included in EWJEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby an EWJEDEC standard or publication m
6、ay De rtner processed and uitimateiy become an ANSUEYI standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this EWJEDEC standard or publication should be addres
7、sed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA 2220 1-3834, (703)907-7560/7559 or www.jedec.org Published by ELECTRONIC INDUSTRIES ALLIANCE 1999 Engineering Department 2500 Wilson Boulevard Arlington, VA 2220 1-3834 “Copyright“ does not apply to JEDEC member co
8、mpanies as they are free to duplicate this document in accordance with the latest revision of JEDEC Publication 2 1 “Manual of Organization and Procedure“. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications or call Global Engineering Documents, USA and Canada
9、(1-800-854-7179), International (303-397-7956) Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the EL4 and may not be reproduced without permission. Organizations may obtain permission to reproduce a iimited number of copies through entering in
10、to a license agreement. For information, contact: Global Engineering Documents 15 Inverness Way East Engiewood. CO 801 12-5704 or call U.S.A. and Canada 1-800-854-7179, International (303) 397-7956 JEDEC Standard No. 5 1-6 INTEGRATED CIRCUIT THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - FORCED CONV
11、ECTION (MOVING AIR) Contents 1 Scope 2 Normative references 3 Definitions, symbols, and abbreviations 4 Specification of environmental conditions 4.1 Wind tunnel specifications 4.1.1 Flow uniformity 4.1.2 Swirl 4.1.3 Turbulence 4.1.4 Unsteadiness 4.1.5 Chiu?i“uer size 4.1.6 Temperature uniformity 4.
12、1.7 Performance verification 4.2 Testboard 4.3 Placement in the test section 4.3.1 Orientation 4.3.2 Measurement 4.3.3 Simultaneous testing 4.4 Test fixture support 4.5 Environmental conditions and measurements 4.5.1 Flow velocity measurement 4.5.2 Ambient temperature measurement 5 Thermal measureme
13、nt procedure and methodology 5.1 K factor calibration 5.2 Test start-up and initial equilibrium verification 5.3 Power level seiection and applying power 5.4 Verification of thermal steady-state and test completion 5.5 Verification of absence of interaction between applied power level and temperatur
14、e- sensitive parameter (optional procedure) 6 Thermal characterization parameters 6.1 Y JT Junction-to-top-center of the package (Optional procedure) 6.2 Y JT Junction-to-board (Optional procedure) 7 Test conditions to be reported Page 1 1 1 2 2 2 2 3 3 4 4 4 4 6 6 6 7 7 7 7 8 9 9 10 10 10 3 J 11 11
15、 11 12 -1- JEDEC Standard No. 5 1-6 INTEGRATED CIRCUIT THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - FORCED CONVECTION (MOVING AIR) Contents (concluded) Page Figures 1 Open circuit wind tunnel 2 minimum clearance 3 Test section 4 Horizontal air flow, horizontal board (Package up) 5 Horizontal air f
16、iow, vertical board orientation 6 Vertical air flow, vertical board 7 Thermocouple location Tables 1 Recriended pO“ kvds 2 Thermal measurement test conditions and data parameters 2 3 4 5 5 6 11 10 12 -11- JEDEC Standard No. 5 1-6 Page 1 INTEGRATED CIRCUIT THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS
17、 - FORCED CONVECTION (MOVING AIR) (From JEDEC Board Ballot JCB-98-103, under the cognizance of the JC-15.1 Committee on Themal Characterization.) 1 Scope This standard specifies the environmental conditions for determining thermal performance of an integrated circuit device in a forced convection en
18、vironment when mounted on a standard test board. The thermal resistance measured using this document is RQJMA or BJMA. This methodology is not meant to and will not predict the performance of a device in an application-specific environment. 2 Normative references The following standards contain prov
19、isions that, through reference in this text, constitute provisions of this standard. At the time of publication, the editions indicated were valid. All standards are subject to evisin, anci pplcs i ageerxnts based ii :his s:dxd are ecruged te ivestigzte the pssiki!i nf “I applying the most recent ed
20、itions of the standards indicated below. JESDS i, “Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Devices)“. This is the overview document for this series of specifications. JESD5 1-1, “Integrated Circuit Thermal Measurement Method - Electrical Test Method“. JESD
21、5 1-2, “Integrated Circuit Thermal Test Method Environmental Conditions - Natural Convection (Still Air). JESDS 1-3, “Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages“. JESDS 1-4, “Themal Test Chip Guideline (Wire Bond Type Chip)“ JESDS 1-7, “High Effective Thermal Con
22、ductivity Test Board for Leaded Surface Mount Packages“ 3 Definitions, symbols, and abbreviations Refer to the documents JESD51, JESDSI-1 and JESD51-2 for a general list of terminology. JEDEC Standard No. 51-6 Page 2 Entrance and Settling Zone 4 Specification of environmental conditions Contraction
23、Section Transition Air Mover.(Fan) 4.1 Wind tunnel specifications Test Section Section A low velocity wind tunnel is shown in figure 1 as an example only. The package and test fixtures are not shown in this example. In most electronic applications, the wind tunnels are normally used at velocities le
24、ss than 10 m/s. The minimum specifications for acceptable wind tunnels are detailed in the following paragraphs. Normally the manufacturer of the wind tunnel will characterize the wind tunnel to certify performance to these specifications. The wind tunnel is characterized without the test board and
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