JEDEC JEP147-2003 Procedure for Measuring Input Capacitance Using a Vector Network Analyzer (VNA)《使用适量网络分析(VNA)测试输入电容的程序》.pdf

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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJEP147OCTOBER 2003JEDECPUBLICATIONProcedure for Measuring InputCapacitance Using a Vector Network Analyzer (VNA) NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approvedthrough the JEDEC Council level and subseque

2、ntly reviewed and approved by the EIA GeneralCounsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purchaser in sele

3、cting and obtaining with minimum delaythe proper product for use by those other than JEDEC members, whether the standard is to be usedeither domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption mayinvolve patents or articles, m

4、aterials, or processes. By such action JEDEC does not assume anyliability to any patent owner, nor does it assume any obligation whatever to parties adopting theJEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specif

5、ication and application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in thestandard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publica

6、tionshould be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard,Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org. Published by JEDEC Solid State Technology Association 2003 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charg

7、e, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Pri

8、nted in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the JEDEC Solid State Technology Association and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license

9、agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Publication No. 147Page 1PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA)(From JEDEC Board Ballot JCB-03-43,

10、formulated under the cognizance of the JC-16 Committee on Interface Technology.)1 ScopeThis procedure is intended for VNA (Vector Network Analyzer) based measurement of pin input capacitance for devices with SSTL (Stub Series Terminated Logic) interface . This procedure does not mandate a specific m

11、ethod for measuring input capacitance. It has only to be considered mandatory if it is explicitly refered to by a component specification in conjunction with a value of an input capacitance defined in such a specification.The procedure outlined below. was written having DDR SDRAM (Double Data Rate S

12、ynchronous Dynamic Random Access Memory) devices in mind. is expected to yield an accuracy of 10% (or 100 fF, whichever is greater) and a accuracy of 10% (or 50 fF, whichever is greater) for measuring capacitance differences (Cdelta). ignores (in its simplified version) the error introduced by the i

13、nductance of the test fixture. ignores the inductance of the input pin. is intended for application frequencies 1 pF. allows S-parameter based de-embedding of the test fixture, if those parameters are known. may be applied to interfaces other than SSTL.2 Equipment requirements and preparation2.1 Req

14、uired hardware- Vector Network Analyzer (e.g. Agilent 8753ES or equivalent) with minimum bandwidth of 3 GHz.- Microwave probes (DC to 40 GHz, (G,S) or (S,G) footprint, 3.5 mm connector compatible, low-loss coaxial technique). Probe needs to support SOL (Short, Open, Load) calibration.JEDEC Publicati

15、on No. 147Page 22 Equipment requirements and preparation (contd)2.1 Required hardware (contd)- Test cable, 120 cm, 20 GHz with 3.5 mm or SMA connectors, with low phase variation (phase change on bending 4 radius of 58 mm)- appropriate torque wrenches- test fixture requirements :- accept components-

16、allow the use of coplanar probes and add minimum parasitics (Cfix 0.5 pF; Lfix 0.5 nH; this will generally allow the simple capacitance calculation outlined in section 3.3)- Probing station for fixing the probe to test fixture- APC 7 mm to male 3.5 mm or SMA connector adapter- Two DC power supplies-

17、 Impedance Standard Substrate, supports SOL calibration, wide pitch range, suitable for microwave probes from DC to 40 GHz, allowing probe (G,S) or (S,G) footprint, in combination with CalKit software for VNA.JEDEC Publication No. 147Page 32 Equipment requirements and preparation (contd)2.2 Measurem

18、ent setupFigure 1 Measurement setup, simple equivalent circuit and S-parameter representationDC Power supply Front Panelbias connectorVNADC Power supplyDUTVDDVDDQVSSVSSQPin under TestfixtureVSSVDDVBIASVDDcableprobeinput port (A, B) of fixtureoutput port (C, D) of fixtureABCDVNA Fixture DUTABDCS11inS

19、11fix S12fixS21fix S22fixmeasured value: S11input port (A, B)CinCfixoutput port (C, D)input port(A, B)output port(C, D)JEDEC Publication No. 147Page 42 Equipment requirements and preparation (contd)2.3 Settings- measurement is performed at 25 oC- start frequency: 6.25 MHz- stop frequency: 2.5 GHz- n

20、umber of points: 400- sweep type: linear- sweep time: Auto- input power: -16 dBm, DC level = VBIAS- set current limit on VBIAS- IF bandwidth: 30 Hz- VDD = VDDQ = 2.5 V (for SSTL_2); VDD = VDDQ = 1.8 V (for SSTL_18)- VBIAS = 1.25 V (for SSTL_2); VBIAS = 0.9 V (for SSTL_18)NOTE 1 frequency sweep is re

21、commended but not requiredNOTE 2 If the nominal voltage VDDQ of the device is not VDD, then this nominal voltage should be applied.NOTE 3 Pins for interfaces other than SSTL may be measured using the same procedure. The values specific for these interfaces need to explicitly be specified in these ca

22、ses along with a reference to this procedure.NOTE 4 “Input power” refers to the setting of the VNA and does not imply a certain power actually being driven into the pin during test.2.4 Calibration- SOL (50 ) JEDEC Publication No. 147Page 53 Measurement procedure3.1 Test fixture measurement1) Place t

23、he test fixture into the probing station.2) Place the probe on the pins of interest, and measure S11 of the test fixture only3) Calculate the impedance Zfix ( f = 100 MHz):4) Calculate test fixture capacitance Cfix: 3.2 Component measurement1) Place the component with test fixture into the probing s

24、tation2) set VDD and VBIAS to the above values3) connect other pins (not under test) to the specified voltage levels as outlined in the device specification (see section 4). Preferably all pins (other than supply pins) are left floating; this allows to measure all pins of interest without change of

25、wiring. 4) place the probe on the pin of interest and measure S113.3 Capacitance calculation1) Calculate the impedance Zterm:2) Calculate the total measured capacitance:3) the parasitic capacitance introduced by the test fixture must be subtracted from Ctotal:Zfix 501 S11+1 S11-=Cfix12 100MHz Im Zfi

26、x() -=Zterm 501 S11+1 S11-=Ctotal12 100MHz Im Zterm() -=Cin Ctotal Cfix=JEDEC Publication No. 147Page 63 Measurement procedure (contd)3.4 S-parameter based de-embedding of fixtureIf the S-parameters Sfix of the fixtures are known (by independent measurement or modelling), a more accurate calculation

27、 using those parameters maybe applied:The above equations may also be used to evaluate whether the simple calculation (3.3) is a reasonable approximation. Generally if the error introduced by the fixture is less than the greater of 3% or 60 fF, the calculation according to section 3.3 seems sufficie

28、nt.4 Example device specificationReference to this procedure must be accompanied by language (in the device specification) determining the state (mode of operation) in which the device should be in. Below in an example for a DDR SDRAM (JESD79) (for reference only):“Input capacitance is measured acco

29、rding to JEP147 with VSS, VSSQ, VDD , VDDQ applied and all other pins (except the pin under test) floating. DQs should be in high impedance state. This may be achieved by pulling CKE to low level.”5 ReferencesGeneral Introduction to the use of S-parameters, Agilent Technologies: Application Note AN

30、154S11inS11 S11fixS12fix S21fix S11 S22fix S11fix S22fix+-=Zin 501S11in+1S11in-=Cin12 100MHz Im Zin() -=Standard Improvement Form JEDEC JEP147 The purpose of this form is to provide the Technical Committees of JEDEC with input from the industryregarding usage of the subject standard. Individuals or

31、companies are invited to submit comments toJEDEC. All comments will be collected and dispersed to the appropriate committee(s). If you can provide input, please complete this form and return to: JEDEC Attn: Publications Department 2500 Wilson Blvd. Suite 220 Arlington, VA 22201-3834 Fax: 703.907.758

32、3 1. I recommend changes to the following: Requirement, clause number Test method number Clause number The referenced clause number has proven to be: Unclear Too Rigid In Error Other 2. Recommendations for correction: 3. Other suggestions for document improvement: Submitted by Name: Phone: Company: E-mail: Address: City/State/Zip: Date: Rev. 09/02