JEDEC JEP139-2000 Constant Temperature Aging to Characterize Aluminum Interconnect Metallization for Stress-Induced Voiding《老化应力松弛特征化铝互连线金属喷镀》.pdf

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1、JEDEC PUBLICATION Constant Temperature Aging to Characterize Aluminum Interconnect Metallization for Stress-Induced Voiding JEP139 DECEMBER 2000 (Reaffirmed: October 2012) JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, review

2、ed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchan

3、geability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted witho

4、ut regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in

5、 JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately b

6、ecome an ANSI standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer

7、 to www.jedec.org under Standards and Documents for alternative contact information. Published by JEDEC Solid State Technology Association 2012 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this

8、material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For informatio

9、n, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Publication No. 139-i-GUIDELINE FOR CONSTANT TEMPERATURE AGING TO CHARACTERIZEALUMINUM INTERCONNECT ME

10、TALLIZATIONS FOR STRESS-INDUCEDVOIDINGCONTENTSPage1 Scope 12 Introduction 12.1 Stress-induced voids 12.2 Void growth 22.3 Technology-dependent factors 22.4 Post processing factors 22.5 Void nucleation factors 32.6 Structures 32.7 Stress temperature 32.8 Void volume 33 Constant temperature aging test

11、 method 43.1 Constant temperature aging for stress-induced voids 43.2 Suggested procedure 43.3 Test structures 53.4 Test conditions, procedures, and measurements 63.5 Data interpretation 74 Precautions and interferences 94.1 Variation of resistance change 94.2 Copper solubility 104.3 Comparisions 10

12、4.4 Thermal cycling 104.5 Peak temperature 104.6 In situ measurements 104.7 Calculated void volume 114.8 Passivation deposition temperature 114.9 Joule heating 115 Datatobereported 126 References 12JEDEC Publication No. 139-ii-JEDEC Publication No. 139Page 1GUIDELINE FOR CONSTANT TEMPERATURE AGING T

13、O CHARACTERIZEALUMINUM INTERCONNECT METALLIZATIONS FOR STRESS-INDUCEDVOIDING(From JEDEC Board ballot JCB-00-31, formulated under the cognizance of the JC-14.2Committee on Wafer-Level Reliability.)1ScopeThis document describes a constant temperature (isothermal) aging method for testing aluminum(Al)

14、metallization test structures on microelectronics wafers for susceptibility to stress-inducedvoiding.This method is valid for metallization/dielectric systems in which the dielectric is deposited ontothe metallization at a temperature considerably above the intended use temperature, and above orequa

15、l to the deposition temperature of the metal.If the metallization is a single-alloy component, such as AlSi or AlCu, the failure criterion of themethod is an open-circuit of the test structure. The failure criterion for layered metallizationswith refractory shunt layers (such as titanium (Ti), titan

16、ium nitride (TiN), tungsten (W), etc.) is apreselected percent increase in resistance of the test structure.The method assumes that void growth and therefore resistance changes can be modeled, asdescribed by Rauch and Sullivan 1, 2, to obtain an acceleration factor for void growth.Although this is a

17、 wafer test, it is not a fast (less than 5 minutes per probe) test. It is intended tobe used for lifetime prediction and failure analysis, not for production Go-NoGo lot checking.2 Introduction2.1 Stress-induced voidsStress-induced voiding, which can occur during processing, storage, and use, is a r

18、eliabilityconcern for microelectronics chips that use Al-based alloys for on-chip wiring. The subject hasbeen extensively reviewed by Okabayashi 3. Susceptible metallizations can grow voids in linesand under or over W studs. For simple metallizations like AlSi, such voids can causecatastrophic failu

19、re. For metallizations of Al layered with a refractory shunt layer, voids causeresistance increases and interact with other failure mechanisms, such as electromigration andmechanical failure, to shorten lifetime.JEDEC Publication No. 139Page 22 Introduction (contd)2.2 Void growthOnce voids have nucl

20、eated, the rate of void growth is controlled primarily by two quantities:1) the tensile stress in the Al, and 2) self diffusivity of the Al. The tensile stress increaseslinearly as temperature decreases below the dielectric deposition temperature, while diffusivityincreases exponentially with temper

21、ature. The product of these two factors produces a peak inthe rate of void growth which is located between the dielectric deposition temperature and usetemperature. Published data indicates that this peak can occur anywhere in the range from 90oCto 300oC 4, 5, 6.2.3 Technology-dependent factorsA var

22、iety of technology-dependent factors define and modify the stress distribution and thediffusivity in the Al. A partial list of such secondary factors includes: Al microstructure and alloy impurities, Al deposition temperature, prior heat treatment, properties of the passivation layer, interfacial ad

23、hesion between the passivation and Al, refractory cladding layers and associated mechanical properties, line dimensions, electrical properties of cladding layer, interfacial diffusivity (Al/SiO2, Al/TiAl3,etc.) metal-etch profile of the line in cross section, layout shape, the presence, configuratio

24、n, and material of inter-level interconnects, passivation deposition temperature, cool-down rate of wafer after last process step, from temperatures comparable to thepassivation deposition temperature, and intermetallic reactions (for layered metallizations).2.4 Post processing factorsAlthough this

25、document is intended to apply primarily to wafers, it should be noted thatadditional factors besides wafer-level processing could influence stress-voiding behavior. Theseinclude, but are not limited to, extended packaging processing and testing, card mountingprocessing, and system assembly.JEDEC Pub

26、lication No. 139Page 32 Introduction (contd)2.5 Void nucleation factorsBesides factors which influence void growth, an additional class of factors exist which influencevoid nucleation. These include several of the factors listed in 2.3. Other considerations shouldinclude the presence of etch residue

27、 contaminants or metal damage (holes, roughness, etc.) aftermetal etch and cleaning, line-width, ratio of grain-size to line width, and the amount of thealloying element (such as Cu) and variations in line widths and grain size distribution.2.6 StructuresTo test the susceptibility of the technology

28、in question, structures which emphasize each extremeof the technology should be designed and evaluated. (See section 3.3 for more discussion.)2.7 Stress temperatureTo evaluate the impact of stress voiding on chip reliability under use conditions, acceleratedtesting is needed to generate voiding. Bec

29、ause the acceleration factor, which depends on stress inthe Al and Al mass transport (diffusivity), can be very strongly affected by the factors listed in2.3, the selection of the temperature for accelerated testing which will maximize voiding is notobvious in advance and must be determined empirica

30、lly.2.8 Void volumeAssuming the oxide behaves elastically, the maximum volume of voiding in a specific structurecan be calculated by assuming that only thermal contraction of the Al is relevant. (See paragraph4.6 in Precautions and Interferences for limitations on this assertion.) Then the maximumvo

31、lume possible for voiding is equal to the volume change for unconstrained Al, and is given byV=3 * T*V,(1)where V is the volume of the interconnect of concern, is the thermal expansion coefficient ofAl (approximately 2510-6K-1), and T is the difference in temperature between the passivationdepositio

32、n temperature and the stress (bake) temperature. If the bake temperature is taken atroom temperature and the passivation deposition temperature is 425oC, for example, then(V/V)max = 3%. Clearly, at higher use temperatures, this relative volume will be less.Observation of voiding in excess of 3% at r

33、oom temperature is likely to mean that some othermechanism in addition to, or besides, stress voiding is involved.JEDEC Publication No. 139Page 43 Constant temperature aging test method3.1 Constant temperature aging for stress-induced voidsThe test method most likely to detect sensitivity to stress

34、voiding and the one most usuallyconducted is constant temperature (isothermal) aging, i.e., annealing or baking at temperaturesbetween the passivation deposition temperature and the intended use temperature of the product.The wafers are baked, cooled periodically to room temperature, and measured fo

35、r any changes inresistance of the structures under test. Some studies have shown that cooling down wafers afterthe last high-temperature process (high temperature meaning comparable to passivationdeposition temperature) can alter the size of the voids nucleated in the Al. However, littlechange in vo

36、id size is expected during cooling down from the test temperature to make resistancemeasurements, or during subsequent reheating. (See 4.3 and 4.4 for related information.)3.2 Suggested procedure (See also 3.2.8 for a decision list)3.2.1 Select ten wafers, for example, from each of three wafer lots

37、(a total of 30 wafers).3.2.2 Measure sheet resistances and line resistances of relevant test structures on these wafers, asreceived, at wafer level for two reasons: to ensure that the measured resistances fall within expected ranges for the structuresinvolved and the applicable design rules and to c

38、ompare these resistance values with those measured during constant temperatureaging.3.2.3 Separate wafers into five groups, each group to be baked at a different temperature (e.g.,175, 200, 225, 250, and 275oC), such that each group contains two wafers from each of the threelots (or a total of six w

39、afers). (If the temperature for peak voiding is not known for themetallization under test, additional temperatures up to the passivation deposition temperaturemay be needed.)3.2.4 Bake (thermally age) the wafers at the specified temperatures and cool in less than 2hrs toroom temperature (see precaut

40、ions in 4.4 and 4.5 on rate of temperature change) for test readouts(e.g., at 24, 48, 100, 250, 500, 750, 1000, 1500, and 2000 h). At each test readout, re-measurethe resistances of each of the structures measured before continuing to bake.3.2.5 Report failures for each readout for each structure. F

41、ailure is defined by a predeterminedresistance increase (e.g., 5%). Plot cumulative failures vs. the log of readout time, assumingfailure times are log-normally distributed.JEDEC Publication No. 139Page 53 Constant temperature aging test method (contd)3.2 Suggested procedure (contd)3.2.6 Count the n

42、umber of voids in stressed parts (from scanning electron microscope (SEM)photos of delayered mazes) to determine void nucleation density in structures of interest, if thevoid density is relevant to the chip design.3.2.7 Determine the lifetime (3.5.5). Optionally, use the acceleration factor (3.5.6)

43、to determinethe lifetime at use conditions from the accelerated stress data.3.2.8 Procedures to be agreed upon before starting (Procedures Summary)Description Ref. ParagraphDefine Bake Temperatures 3.2.3, 3.4.2Define Measurement Intervals (test points) 3.2.4, 3.4.3Define Failure Criteria (fractional

44、 % R change) 3.2.5Define Lot and Replication Samples (wafer samples, n-samples/wafer, etc.) 3.2.1, 3.4.2Define StructureLine Configuration (straight, surpentine, W-studs. . .)Width or (line-width/grainsize) ratio 3.3.3Line Length 3.3.1, 3.3.2Stud Size hence the adviseddistribution of widths.3.3.2 Lo

45、ng, narrow lines (serpentines, mazes) provide sufficient length to insure that voidnucleation sites will exist, and will produce voids if the metallization/insulator system issusceptible. The change in resistance with time at stress temperature of such structures providesa good measure of the relati

46、ve average void density in the line.JEDEC Publication No. 139Page 63 Constant temperature aging test method (contd)3.3 Test structures (contd)3.3.2.1 However, if the narrowest lines are primarily bamboo in structure, the void density maybe lower than for wider lines and the corresponding resistance

47、increase will be smaller. In thiscase, shorter lines are useful because they will manifest a higher fractional change in resistancewhen voiding is present. However, fewer of them will register any resistance shift at all becauseof the spatial distribution in nucleation sites.3.3.2.2 In addition, str

48、ess voiding in these structures is often sensitive to line-to-line separationin the maze; therefore, single, long, isolated lines should also be available. The line-to-lineseparation sensitivity can be caused by several factors, among which are: line width variations caused by variations in etching

49、with metal density, variations in oxide density due to interline aspect ratio and fill, and additional lateral stress arising from the presence of neighboring metal.3.3.3 Multiple line widths are needed to evaluate sensitivity to the ratio of grain-size to line-width. These widths can be 1.1, 1.3, and 2.0 times the minimum line width or the average grainsize.3.3.4 For multi-level metallizations, structures having W-studs underlying and/or overlying theline structures are effective because W has a larger thermal expansion coefficient than SiO2.Hence, th