JEDEC JEP128-1996 Guide for Standard Probe Pad Sizes and Layouts for Wafer-Level Electrical Testing《Wafer-Level电测的标准探针垫大小和布置指南》.pdf

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1、a) N EINJEDEC PUBLICATION Guide for Standard Probe Pad Sizes and Layouts for Wafer-Level Electrical Testing EIALJEP128 NOVEMBER 1996 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT NOTICE EINJEDEC Standards and Publications contain material that has been prepared, progressively reviewed, an

2、d approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. EINJEDEC Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturen and purchases, facilitating interchangeability and im

3、provement of products, and assisting the purchaser is selecting and obtaining with minimum delay the proper product for his particular need. Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC from manufacturing or selling products not conforming to such st

4、andards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members, whether the standard is to be used either domestically or internationally. EINJEDEC Standards and Publications are adopted without regard to whether their adoption may involve patents or

5、articles, materials, or processes, By such action, EINJEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the EINJEDEC Standards or Publications. The information included in EINJEDEC Standards and Publications represents a sound app

6、roach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the EINJEDEC organization there are procedures whereby an EIMJEDEC Standard or Publication may be further processed and ultimately becomes an ANSIIEIA Standard. Inquiries, comments,

7、 and suggestions relative to the content of this EINJEDEC Standard or Publication should be addressed to the JEDEC Executive Secretary at EIA Headquarters, 2500 Wilson Boulevard, Arlington, VA 22201. Published by ELECTRONIC INDUSTRIES ASSOCIATION 1996 Engineering Department 2500 Wilson Boulevard Arl

8、ington, VA 22201 “Copyright“ does not appiy to JEDEC member companies as they are free to duplicate this document in accordance with the latest revision of the JEDEC Publication 21 “Manual of Organization and Procedure“. PRICE: Please refer to the current Catalog of EIA, JEDEC, and TIA STANDARDS and

9、 ENGINEERING PUBLICATIONS or call Global Engineering Documents, USA and Canada (1-800-854-7179) International (303-397-7956) Printed in U.S.A. All rights resewed EIA JEPL26 b 3234600 0578818 O01 EINEDEC Publication No. 128 GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER-LEVEL ELECTRICAL TES

10、TING CONTENTS 1 Scope 2 Introduction: significance and use 3 Designguides 3.1 Size of contact pads 3.2 Double-column pad layout array 3.3 Single-column pad layout array 3.4 Separation of pad arrays on the wafer Page 1 1 2 2 2 5 5 -1- EIA JEP128 96 3234600 0578819 T48 EINJEDEC Publication 128 -11- EI

11、A JEPL28 b 3234600 0578820 bT m . EINJEDEC Publication No. 128 Page 1 GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER-LEVEL ELECTRICAL TESTING (From JEDEC Ballot JCB-96-27, formulated under the cognizance of JC-14.2 Committee on Wafer-Level Reliability.) 1 Scope This guide applies to double

12、- and single-column arrays of metal probe pads, on a semiconductor wafer or chip, that are electrically connected to one or more test structures. The use of this guide will make necessary only two standard wafer-probe cards, one with a 1-by- 16 and the other with a 2-by-16 standard array of probe ti

13、ps to make contact with probe pads. This guide is intended, in particular, to facilitate and expedite wafer-level electrical testing by laboratories participating in interlaboratory experiments conducted by the JC- 14.2 Committee. This guide .is intended, in general, to facilitate and expedite wafer

14、-level electrical testing of test structures, when using a wafer-probe card to make electrical contact to these structures. The use of this guide will impose some restrictions on how test structures may be grouped within and near the area defined by the array of pads. 2 Introduction: significance an

15、d use It is usefl to have a standard for the size and layout of the probe pads of test structures that are to be electrically characterized or tested at the wafer level. Having such a standard design affords efficient and cost-effective use of wafer-probe stations because its widespread use leads to

16、 the need for a minimum number of probe cards and card changes to accommodate the various test structures that may need to be tested. The use of a standard for the layout of probe pads is important for conducting interlaboratory experiments to evaluate or develop standard measurement methods that in

17、volve test-stmcture measurements or tests. When a probe card required by a test structure is not readily available, manual probing is an option that presents significant potential for damage to the test structure. Damage to structures involved in interlaboratory experiments can lead to serious delay

18、s in the conduct and analysis of such experiments. . EIA JEP328 76 3234600 0578823 bTb EINJEDEC Publication No. 128 Page 2 3 Design guides The probe pads are designed to be probed by probe cards having one of two standard probe arrays: 16 probe tips arranged in a column at 160 pm intervals, and two

19、such columns in a 2-by- 16 arrangement where the separation of the two columns is dictated by the need to contact a parallel column of pads that have a center-to-center separation of 160 pm. NOTE - An optimum separation of the two columns of probe tips may involve a somewhat greater separation than

20、160 pm to accommodate inward movements of the probes as they make contact with the metal pad. 3.1 Size of contact pads The minimum pad size shall be 80 pm on a side. NOTE - If the test structures are to be covered with a passivation film, the selection of the size of the opening in the passivation l

21、ayer over the metal pad is left to the user. It is generally desirable to maximize this opening (without exposing the edges of the metal pad) to facilitate probing and wire bonding. 3.2 Double-column pad layout array 3.2.1 The pads shall be arranged in two columns and the center-to-center separation

22、 of the pads in both horizontal and the vertical directions shall be 160 pm. See figure 1. NOTE - If a pad size larger than 80 pm on a side is selected (see 3.1), adequate separation between adjacent pad edges should be provided to avoid possible short circuits between adjacent wire bonds (if used).

23、 Adequate separation between the pads and any adjacent-running features of the test structures should be provided for to reduce the possibility of damage to these features by accidental skidding of the other probe off the pad. 3.2.2 The pads shall be numbered in 2-by-16 units as shown in figure 2. N

24、OTE - If a substrate contact is used in the test, the pad number of this contact should correspond to the probe pin that is electrically connected to the wafer stage of the probing station. EIA JEPL28 9b m 3234600 0578822 532 m I I I 7- EINJEDEC Publication No. 128 Page 3 1 Figure 1 -Drawing of a po

25、rtion of a 2-by-16 array of bondinglprobe pads. 3.2.3 To avoid the possibility of confusion because of the 180 rotational symmetry, pad #1 shall be shaped differently from the other pads (as illustrated in figure 2) or some feature shall be included that makes pad #1 easily recognizable when using t

26、he optics of the probe station. 3.2.4 If the number of pad pairs is less than 16, space on the wafer should be free of features for the placement of a 2-by-16 probe card, where the probe tips are designed to contact the standard probe-pad array described in 3.2.1. NOTE - To prevent contamination of

27、the probe tips, it is recommended that a metal probe pad always be located where a probe would land on the wafer or chip. EIA JEPL28 96 3234600 0578823 477.1 EINJEDEC Publication No. 128 A Page 4 . El El El El m El Figure 2 -Pad numbering scheme for a 2-by-16 unit 4 EIA JEPL28 9b W 3234600 0578824 3

28、05 - EINJEDEC Publication No. 128 Page 5 3.2.5 If the number of pad pairs is larger than 16, the contacts for any one test structure must be contained completely within the first or within any. subsequent set of 16 pad pairs that would serve to extend the column of pad pairs. 3.3 Single-column pad l

29、ayout array 3.3.1 The pads shall be aligned in one column and the center-to-center separation of the pads in the column shall be 160 pm. See 3.2.1 Note. 3.3.2 The pads shall be numbered in units of 16. See 3.2.2. Note. 3.3.3 To avoid the possibility of confusion because of the 180“ rotational symmet

30、ry, pad #I shall be shaped differently from the other pads (as illustrated in figure 2) or some feature-shall be included that makes pad #1 easily recognizable when using the optics of the probe station. 3.3.4 If the number of pads is less that 16, space on the wafer shall be free of features for th

31、e placement of a I-by-16 probe card designed to contact the line of pads described in 3. See 3.2.4 Note. 3.3.5 If the number of pads is larger than 16, the contacts for any one test structure must be contained completely within the first or within any subsequent set of 16 pads that would serve to ex

32、tend the column of pads. 3.4 Separation of pad arrays on the wafer If the pad arrays are to be replicated on the wafer or chip, they shall be spaced at regular intervals in either horizontal or vertical directions, or both. . - EIA JEPL28 96 m 323LibOO 0578825 241 m EIAJEDEC Publication No. 128 Page 6 EIA JEP128 96 3234600 0578826 188 M