JEDEC JEP122H-2016 Failure Mechanisms and Models for Semiconductor Devices.pdf
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1、 JEDEC PUBLICATION Failure Mechanisms and Models for Semiconductor Devices JEP122H (Revision of JEP122G, October 2011) SEPTEMBER 2016 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Boa
2、rd of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products,
3、 and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adop
4、tion may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications repr
5、esents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to b
6、e in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and
7、Documents for alternative contact information. Published by JEDEC Solid State Technology Association 2016 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the
8、 individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technolo
9、gy Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Publication No. 122H -i- FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES Contents Page Foreword iii Introduction iii 1 Scope 1 2 Ter
10、ms and definitions 1 3 Inclusions, deliberate omissions, and resources 5 4 The basic thermal acceleration equation 9 5 Models for common failure mechanisms 9 FEoL Failure Mechanisms 5.1 Time-Dependent Dielectric Breakdown (TDDB) gate oxide 9 5.2 Hot Carrier Injection (HCI) 14 5.3 Negative Bias Tempe
11、rature Instability (NBTI) 17 5.4 Surface inversion (mobile ions) 19 5.5 Floating-Gate Nonvolatile Memory Data Retention 21 5.6 Localized Charge Trapping Nonvolatile Memory Data Retention 29 5.7 Phase Change (PCM) Nonvolatile Memory Data Retention 31 BEoL Failure Mechanisms 5.8 Time-Dependent Dielect
12、ric Breakdown (TDDB) ILD/Low-k/Mobile Cu ion 34 5.9 Aluminum Electromigration (Al EM) 43 5.10 Copper Electromigration (Cu EM) 46 5.11 Aluminum and Copper Corrosion 48 5.12 Aluminum Stress Migration (Al SM) 53 5.13 Copper Stress Migration (Cu SM) 55 Packaging/Interfacial Failure Mechanisms 5.14 Fatig
13、ue failure due to temperature cycling and thermal shock 58 5.15 Interfacial failure due to temperature cycling and thermal shock 63 5.16 Intermetallic and oxidation failure due to high temperature 66 5.17 Tin Whiskers 68 5.18 Ionic Mobility Kinetics (PCB) Component Cleanliness 72 Statistics and Mode
14、ling Parameter Determination 5.19 Reliability data/analysis 75 5.20 Design of Experiments (DOE) for determination of modeling parameters 80 6 Activation energies and modeling factors 82 Annexes Annex A List of references 87 Annex B Differences between JEP122H and JEP122G 103 JEDEC Publication No. 12
15、2H -ii- FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES Contents Figures Page 5.1-1 Photograph of TDDB breakdown in a gate oxide mid-gate 13 5.5-1 (a) Example of failure mechanisms scenario affecting VT during data retention (from 5.5.16), and (b) extraction of Eaa for each mechanism (from 5
16、.5.15). 22 5.5-2 (a) Spectrum of detrapping time constants immediatly after cycling (black curve) and during data retention (red curves), and (b) Resulting VT(tR) transient. 25 5.5-3 (a) Comparison of time constant spectra between uniform cycling of duration tcycand an equivalent cycling where all t
17、he delays are lumped in a single wait of duration A tcycprior to the bake phase, and (b) Resulting VT(tR) transients. A = 0.2 results in similar VTloss during data retention 27 5.5-4 Extrapolation of SILC bit error rate 28 5.8-1 Time-Dependent Dielectric Breakdown (TDDB) in various dielectrics 35 5.
18、8-2 Metal stack cross section/schematic 37 5.8-3 Normal distribution of breakdown voltage 38 5.8-4 Copper short/extrusion 39 5.9-1 Examples of Aluminum Electromigration 45 5.10-1 Examples of Copper Electromigration 48 5.11-1 Aluminum bond pad corrosion 52 5.11-2 Electrochemical reaction 52 5.11-3 Co
19、rrosion rate versus surface mobility 52 5.12-1 Examples of Aluminum Stress Migration 55 5.13-1 Examples of Copper Stress Migration 57 5.14-1 Examples of temperature cycling/thermal shock damage 62 5.15-1 Example of interfacial delamination after temperature cycling 65 5.17-1 SEM of Tin Whiskers on M
20、atte Tin plated Alloy 42 leads 5.16.4 71 5.17-2 Optical Image of a Tin Whisker growing from Relay lead to case 5.16.3 71 5.17-3 FIB - matte tin whisker structure from a temperature cycled specimen 5.16.5 71 5.17-4 Optical Image - Tin Whisker growing from SAC 305 solder over Alloy 42 - matte tin 71 5
21、.17-5 Optical image of Tin Whisker on a copper coupon with matte tin plating 5.16.4 71 5.17-6 8 mm long Tin Whisker growing from a bracket holding electronics in a frame. 71 5.17-7 Tin Whisker breaking through 10 m Uralane 5750 coating (9 yr office storage) 5.16.3 71 5.18-1 Resistor corroded open du
22、e to trapped MSA residues in epoxy surface 3 73 5.18-2 Electrochemical migration between leads on a QFP 73 5.18-3 Leakage and corrosion problems with residues on tinned leads due to aggressive flux 74 5.18-4 Leakage square brackets enclose citation numbers. All equation, citation, and figure numbers
23、 include the subclause number so that individual clauses can be modified without disturbing other clauses, except for page numbers. Thus, (5.3.2) is the 2nd equation in 5.3 and 5.11.5 is the 5th citation in 5.11. The citations can be found in Annex A. JEDEC Publication No. 122H -iv- JEDEC Publicatio
24、n No. 122G Page 1 FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES (From JEDEC Board Ballot JCB-01-97, JCB-03-39, JCB-08-61, JCB-09-19, JCB-10-64, JCB-11-74, and JCB-16-32, formulated under the cognizance of JC-14.1 Subcommittee on Reliability Test Methods for Packaged Devices.) 1 Scope This
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