DLA SMD-5962-98620-1999 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS OCTAL DUAL SUPPLY CONFIGURABLE VOLTAGE INTERFACE TRANSCEIVER WITH THREE-STATE OUTPUTS MONOLITHIC SILICON《微型电路 数字型 低压CM.pdf

《DLA SMD-5962-98620-1999 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS OCTAL DUAL SUPPLY CONFIGURABLE VOLTAGE INTERFACE TRANSCEIVER WITH THREE-STATE OUTPUTS MONOLITHIC SILICON《微型电路 数字型 低压CM.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-98620-1999 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS OCTAL DUAL SUPPLY CONFIGURABLE VOLTAGE INTERFACE TRANSCEIVER WITH THREE-STATE OUTPUTS MONOLITHIC SILICON《微型电路 数字型 低压CM.pdf（20页珍藏版）》请在麦多课文档分享上搜索。

1、REVISIONSLTR DESCRIPTION DATE (YR -MO -DA) APPROVEDREVSHEETREVSHEET 15 16 17 18 19REV STATUS REVOF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14PMIC N/A PREPARED BY Joseph A. KerbyDEFENSE SUPPLY CENTER COLUMBUSSTANDARDMICROCIRCUITDRAWINGCHECKED BYCharles F. Saffle, Jr.COLUMBUS, OHIO 43216THIS DRAWIN

2、G IS AVAILABLEFOR USE BY ALLDEPARTMENTSAPPROVED BYMonica L. Poelking MICROCIRCUIT, DIGITAL, LOW VOLTAGE CMOS,OCTAL DUAL SUPPLY CONFIGURABLE VOLTAGEAND AGENCIES OF THEDEPARTMENT OF DEFENSE DRAWING APPROVAL DATE99-02-19INTERFACE TRANSCEIVER WITH THREE-STATEOUTPUTS, MONOLITHIC SILICONAMSC N/A REVISION

3、LEVEL SIZEA CAGE CODE 67268 5962-98620SHEET 1 OF 19DSCC FORM 2233APR 97 5962 -E126-99DISTRIBUTION STATEMENT A . Approved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA 5

4、962-98620DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000 REVISION LEVEL SHEET 2DSCC FORM 2234APR 971. SCOPE1.1 Scope . This drawing documents two product assurance class levels consisting of high reliability (device classes Q andM) and space application (device class V). A choice of case out

5、lines and lead finishes are available and are reflected in the Partor Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.1.2 PIN . The PIN is as shown in the following example:5962 - 98620 01 Q K XFederal RHA Device Device Case Le

6、ad stock class designator type class outline finishdesignator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3)/ Drawing number1.2.1 RHA designator . Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and aremarked with the appropriate RHA de

7、signator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix Aspecified RHA levels and are marked with the appropriate RHA designator. A dash ( -) indicates a non -RHA device.1.2.2 Device type(s) . The device type(s) identify the circuit function as follows:Device type Generic number

8、 Circuit function01 54LVXC4245 Octal dual supply configura ble voltage interfacetransceiver with three-state outputs1.2.3 Device class designator . The device class designator is a single letter identifying the product assurance level asfollows:Device class Device requirements documentationM Vendor

9、self -certification to the requirements for MIL-STD-883 compliant,non -JAN class level B microcircuits in accordance with MIL-PRF-38535,appendix AQ or V Certi fication and qualification to MIL-PRF-385351.2.4 Case outline(s) . The case outline(s) are as designated in MIL-STD-1835 and as follows:Outli

10、ne letter Descriptive designator Terminals Package styleK GDFP2-F24 or CDFP3-F24 24 Flat packL GDIP3-T24 o r CDIP4-T24 24 Dual-in-line3 CQCC1-N28 28 Square leadless chip carrier 1 /1.2.5 Lead finish . The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appen

11、dixA for device class M.1 / This package is not available from an approved source of supply as of the date of this drawing.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA 5962-98620DEFENSE SUPPLY CENTER COLUMBUSCOLUM

12、BUS, OHIO 43216-5000 REVISION LEVEL SHEET 3DSCC FORM 2234APR 971.3 Absolute maximum ratings . 1 / 2 / 3 /Supply voltage range (V CCA , V CCB ) . -0.5 V dc to +7.0 V dcDC input voltage range (V IN ) -0.5 V dc to V CCA + 0.5 V dcDC input / output voltage range, An (V I/O ) -0.5 V dc to V CCA + 0.5 V d

13、cDC input / output voltage range, Bn (V I/O ) -0.5 V dc to V CCB + 0.5 V dcDC input diode current (I IK ) 20 mADC output diode current (I OK ) . 50 mADC output source or sink current (I O ) (per pin) . 50 mADC V CC or GND current . 200 mAMaximum power dissipation (P D ) 500 mWStorage temperature ran

14、ge (T STG ) -65 C to +150 CLead temperature (soldering, 10 seconds) . +300 CThermal resistance, junction -to -case ( JC ) See MIL -STD -1835Junction temperature (T J ) +175 C 4 /1.4 Recommended operating conditions . 2 / 3 / 5 /Supply voltage range (V CCA ) +4.5 V dc to +5.5 V dcSupply voltage range

15、 (V CCB ) +2.7 V dc to +5.5 V dcInput voltage range (V IN ) . +0.0 V dc to V CCAInput / output voltage range, An (V I/O ) +0.0 V dc to V CCAInput / output voltage range, Bn (V I/O ) +0.0 V dc to V CCBMinimum high level input voltage, An, T/R, OE (V IH ) +2.0 V dcMaximum low level input voltage, An,

16、T/R, OE (V IL ) . +0.8 V dcMinimum high level input voltage, Bn (V I H ):2.7 V V CCB 3.6 V +2.0 V dc3.6 V 1 MHz.b. t r , t f = 3 ns 1.0 ns. For input signal generators incapable of maintaining these values of t r and t f , the 3.0 ns limit may be increased up to 10 ns, as needed, maintaining the 1.0

17、 ns tolerance and guaranteeing the results at 3.0 ns 1.0 ns; skew between any two switching input signals (t sk ): 250ps.FIGURE 4. Ground bounce load circuit and waveforms .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGS

18、IZEA 5962-98620DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000 REVISION LEVEL SHEET 14DSCC FORM 2234APR 97An to BnNOTES:1. When measuring t PLH and t PHL : V TEST = open.2. When measuring t PLZ and t PZ L : V TEST = 2 x V CCB .3. When measuring t PHZ , t PZH : V TEST = GND.4. The t PZL and t

19、 PLZ reference waveform is for the output under test with internal conditions such that the output is at V OLexcept when disabled by the output enable control. The t PZ H and t PHZ reference waveform is for the output under test with internal conditions such that the output is at V OH except when di

20、sabled by the output enable control.5. C L = 50 pF minimum or equivalent (includes test jig and probe capacitance).6. R L = 500 or equivalent.7. R T = 50 or equivalent.8. Input signal from pulse generator: V IN = 0.0 V to 3.0 V; PRR 10 MHz; t r 3.0 ns; t f 3.0ns; t r and t f shall be measured from 0

21、.3 V to 2.7 V and from 2.7 V to 0.3 V, respectively; duty cycle = 50 percent.9. Timing parameters shall be tested at a minimum input frequency of 1 MHz.10. The outputs are measured one at a time with one transition per measurement.FIGURE 5. Switching waveforms and test circuit .Provided by IHSNot fo

22、r ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA 5962-98620DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000 REVISION LEVEL SHEET 15DSCC FORM 2234APR 97Bn to AnNOTES:1. When measuring t PLH and t PHL : V TEST = open.2. When measurin

23、g t PLZ and t PZL : V TEST = 2 x V CCA .3. When measuring t PHZ , t PZH : V TEST = GND.4. The t PZL and t PLZ reference waveform is for the output under test with internal conditions such that the output is at V OLexcept when disabled by the output enable control. The t PZH and t PHZ reference wavef

24、orm is for the output under test with internal conditions such that the output is at V OH except when disabled by the output enable control.5. C L = 50 pF minimum or equivalent (includes test jig and probe capacitance).6. R L = 500 or equivalent.7. R T = 50 or equivalent.8. Input signal from pulse g

25、enerator: V IN = 0.0 V to V CC ; PRR 10 MHz; t r 3.0 ns; t f 3.0ns; t r and t f shall be measured from 10% of V CC to 90% of V CC and from 90% V CC to 10% of V CC , respectively; duty cycle = 50 percent.9. Timing parameters shall be tested at a minimum input frequency of 1 Mhz.10. The outputs are me

26、asured one at a time wi th one transition per measurement.FIGURE 5. Switching waveforms and test circuit - Continued.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA 5962-98620DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, O

27、HIO 43216-5000 REVISION LEVEL SHEET 16DSCC FORM 2234APR 974. QUALITY ASSURANCE PROVISIONS4.1 Sampling and inspection . For device classes Q and V, sampling and inspection procedures shall be in accordance withMIL-PRF-38535 or as modified in the device manufacturers Quality Management (QM) plan. The

28、modification in the QM planshall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall bein accordance with MIL-PRF-38535, appendix A.4.2 Screening . For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and

29、 shall be conductedon all devices prior to qualification and technology conformance inspection. For device class M, screening shall be inaccordance with method 5004 of MIL -STD -883, and shall be conducted on all devices prior to quality conformance inspection.4.2.1 Additional criteria for device cl

30、ass M .a. Burn -in test, method 1015 of MIL -STD -883.(1) Test cond ition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revisionlevel control and shall be made available to the preparing or acquiring activity upon request. The test circuit shallspecify the in

31、puts, outputs, biases, and power dissipation, as applicable, in accordance with the intent specifiedin test method 1015.(2) T A = +125 C, minimum.b. Interim and final electrical test parameters shall be as specified in table II herein.4.2.2 Additional criteria for device classes Q and V .a. The burn

32、 -in test duration, test condition and test temperature, or approved alternatives shall be as specified in thedevice manufacturers QM plan in accordance with MIL-PRF-38535. The burn -in test circuit shall be maintainedunder document revision level control of the device manufacturers Technology Revie

33、w Board (TRB) in accordancewith MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuitshall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specifiedin test method 1015 of MIL-STD-883.b.

34、 Interim and final electrical test parameters shall be as specified in table II herein.c. Additional screening for device class V beyond the requirements of device class Q shall be as specified inMIL-PRF-38535, appendix B.4.3 Qualification inspection for device classes Q and V . Qualification inspec

35、tion for device classes Q and V shall be inaccordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and hereinfor groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).4.3.1 Electrostatic discharge sensitivity qualification inspection . Electrosta

36、tic discharge sensitivity (ESDS) testing shall beperformed in accordance with MIL -STD -883, method 3015. ESDS testing shall be measured only for initial qualification andafter process or design changes which may affect ESDS classification.4.4 Conformance inspection . Technology conformance inspecti

37、on for classes Q and V shall be in accordance withMIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 ofMIL-PRF-38535 permits alternate in -line control testing. Quality confor mance inspection for device class M shall be inaccordance with MIL-P

38、RF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall bethose specified in method 5005 of MIL -STD -883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).Provided by IHSNot for ResaleNo reproduction or networking permitted with

39、out license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA 5962-98620DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000 REVISION LEVEL SHEET 17DSCC FORM 2234APR 97TABLE II. Electrical test requirements .Test requirements Subgroups(in accordance withMIL-STD-883,method 5005, table I)Subgroups(in

40、accordance withMIL-PRF-38535, table III)Deviceclass MDeviceclass QDeviceclass VInterim electricalparameters (see 4.2)- - - - - - 1Final electricalparameters (see 4.2)1 / 1, 2, 3, 7,8, 9, 10, 111 / 1, 2, 3, 7,8, 9, 10, 112 / 1, 2, 3, 7,8, 9, 10, 11Group A testrequirements (see 4.4)1, 2, 3, 4, 7,8, 9,

41、 10, 111, 2, 3, 4, 7,8, 9, 10, 111, 2, 3, 4, 7,8, 9, 10, 11Group C end-point electricalparameters (see 4.4)1, 2, 3 1, 2, 3 1, 2, 3, 7,8,9, 10, 11Group D end-point electricalparameters (see 4.4)1, 2, 3 1, 2, 3 1, 2, 3Group E end-point electricalparameters (see 4.4)1, 7, 9 1, 7, 9 1, 7, 91 / PDA appli

42、es to subgroup 1.2 / PDA applies to subgroups 1 and 7.4.4.1 Group A inspectiona. Tests shall be as specified in table II herein.b. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 2 herein. The testvectors used to verify the truth table shall, at a

43、minimum, test all functions of each input and output. All possible inputto output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2, herein. For deviceclasses Q and V, subgroups 7 and 8 shall include verifying the functionality of the device.c. C IN , C I

44、/O , and C PD shall be measured only for initial qualification and after process or design changes which may affectcapacitance. C IN and C I/O shall be measured between the designated terminal and GND at a frequency of 1 MHz. Thistest may be performed at 10 MHz and guaranteed, if not tested, at 1 MH

45、z. C PD shall be tested in accordance with thelatest revision of JEDEC Standard No. 20 and table I herein. For C IN , C I/O , and C PD , test all applicable pins on fivedevices with zero failures.For C IN and C I/O , a device manufacturer may qualify devices by functional groups. A specific function

46、al group shall becomposed of function types, that by design, will yield the same capacitance values when tested in accordance withtable I, herein. The device manufacturer shall set a functional group limit for the C IN and C I/O tests. The devicemanufacturer may then test one device function from a

47、functional group, to the limits and conditions specified herein. All other device functions in that particular functional group shall be guaranteed, if not tested, to the limits andconditions specified in table I, herein. The device manufacturers shall submit to DSCC-VA the device functions listedin

48、 each functional group and test results for each device tested.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA 5962-98620DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000 REVISION LEVEL SHEET 18DSCC FORM 2234APR 97d. Ground and V CC bounce tests are required for all device classes. These tests shall be performed only for initialqualification, after process or design changes which may affect the performance of the device, and any changes to thetest fixture. V OLP , V OLV , V OHP