DLA SMD-5962-89743 REV B-2012 MICROCIRCUIT DIGITAL HIGH SPEED CMOS HEX D-TYPE FLIP-FLOP WITH RESET TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add footnotes to figure 4, test circuit and switching waveforms. Update boilerplate in accordance with MIL-PRF-38535 requirements. Editorial changes throughout. PHN 06-03-22 Thomas M. Hess B Update boilerplate paragraphs to the current MIL-PRF-38

2、535 requirements. - LTG 12-04-19 Thomas M. Hess REV SHEET REV SHEET REV STATUS REV B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY James E. Nicklaus DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS

3、 DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Thomas J. Riccuiti APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, HEX D-TYPE FLIP-FLOP WITH RESET, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 89-11

4、-02 REVISION LEVEL B SIZE A CAGE CODE 67268 5962-89743 SHEET 1 OF 11 DSCC FORM 2233 APR 97 5962-E317-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89743 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 RE

5、VISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following

6、 example: 5962-89743 01 E A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HCT174 Hex D-type flip-flops with reset, TTL compati

7、ble inputs. 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style C CDIP3-T16 16 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum rat

8、ings. 1/ 2/ 3/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC+ 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc DC input diode current (IIK) . 20 mA DC output diode current, (IOK) 20 mA DC output drain current, (IOUT) . 25 mA DC VC

9、Cor GND current (ICC, IGND) . 50 mA Storage temperature range (TSTG) -65C to +150C Maximum power dissipation (PD) . 500 mW 4/ Lead temperature (soldering, 10 seconds) . +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) . +175C 1.4 Recommended operating cond

10、itions. 2/ 3/ Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Input voltage range (VIN) 0.0 V dc to VCCOutput voltage range (VOUT) . 0.0 V dc to VCCCase operating temperature range (TC) . -55C to +125C Input rise or fall time (tr, tf), VCC= 4.5 V . 0 to 500 ns _ 1/ Stresses above the absolute maxi

11、mum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ The limits for the parameters specified herein shall apply over the full specified VC

12、Crange and case temperature range of -55C to +125C. 4/ For TA= +100C to +125C, derate linearly at 12 mW/C Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89743 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990

13、REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions - Continued. 2/ 3/ Minimum clock frequency (fMAX), VCC= 4.5 V: TC= +25C . 25 MHz TC= -55C to +125C . 17 MHz Minimum clock pulse width high or low, (tw), VCC= 4.5 V: TC= +25C . 20 ns TC= -55C to +125C . 30 ns Minimum

14、setup time data to clock, (ts), VCC= 4.5 V: TC= +25C . 16 ns TC= -55C to +125C . 24 ns Minimum hold time data to clock, (th), VCC= 4.5 V: TC= +25C . 5 ns TC= -55C to +125C . 5 ns Minimum pulse width MR low, (tw), VCC= 4.5 V: TC= +25C . 25 ns TC= -55C to +125C . 38 ns Minimum removal time MR to clock

15、, (trem), VCC= 4.5 V: TC= +25C . 12 ns TC= -55C to +125C . 18ns 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of

16、these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Elec

17、tronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order

18、Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. JEDEC SOLID ST

19、ATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No. 7 - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite

20、 240-S Arlington, VA 22201). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has

21、been obtained. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89743 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The i

22、ndividual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been gr

23、anted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to th

24、e requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design,

25、 construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be

26、as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Test circuit and switching waveforms. The test circuit and switching waveforms shall be as specified on figure 4. 3.3 Electr

27、ical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specif

28、ied in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking

29、of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. Th

30、e compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved sou

31、rce of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certi

32、ficate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this

33、drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Pr

34、ovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89743 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol

35、Test conditions 1/ -55C TC +125C unless otherwise specified 1/ Group A subgroups Limits Unit Min Max High level output voltage VOHVCC= 4.5 V VIN= VIH= 2.0 V or VIL= 0.8 V IOH= -20 A 1, 2, 3 4.4 V IOH= -4.0 mA 1, 2, 3 3.7 V Low level output voltage VOLIOL= 20 A 1, 2, 3 0.1 V IOL= 4.0 mA 1, 2, 3 0.5 V

36、 High level input voltage 2/ VIHVCC= 4.5 V 1, 2, 3 2.0 V Low level input voltage 2/ VIL1, 2, 3 0.8 V Input leakage current IIL, IIHVCC= 5.5 V, VIN= VCCor GND 1, 2, 3 1.0 A Quiescent supply current ICCVCC= 4.5 V, VIN= VCCor GND 1, 2, 3 160 A Additional quiescent supply current ICCVIN = 2.4 V 05 0.5 V

37、, any 1 input, VIN= VCCor GND, all other inputs VCC= 5.5 V 1, 2, 3 3 mA Input capacitance CINSee 4.3.1c 4 10 pF Functional tests VCC= 4.5 V, see 4.3.1d 7, 8 Propagation delay time, clock to output tPHL, tPLH VCC= 4.5 V, CL= 50 pF See figure 4 9 40 ns 10, 11 60 Propagation delay time, MR to output tP

38、HL 9 44 10, 11 66 Output transition time 3/ tTLH, tTHL9 15 10, 11 22 1/ For a power supply of 5.0 V 10%, the worst case output voltage (VOHand VOL) occur for HCT at VCC= 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst case VIHand VILoccur at VCC= 5.5 V and 4.5 V,

39、respectively. 2/ The VIHand VILtests are not required, and shall be applied as forcing function for VOHor VOLtests. 3/ Transition time (tTLH, tTHL), if not tested, shall be guaranteed to the limits specified in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without lic

40、ense from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89743 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 Terminal number Terminal symbol Terminal number Terminal symbol 1 MR 9 CP 2 Q0 10 Q3 3 D0 11 D3 4 D1 12 Q4 5 Q1 13 D4 6 D2 14 D5 7 Q2 15 Q5

41、 8 GND 16 VCCFIGURE 1. Terminal connections. Inputs Output MR CP Dn Qn L X X L H H H H L L H L X Q0H = High voltage level L = Low voltage level = Low to high transition X = Immaterial Q0= Level before the indicated steady state input conditions were established. FIGURE 2. Truth table. Provided by IH

42、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89743 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or

43、networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89743 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 FIGURE 4. Test circuit and switching waveforms. Provided by IHSNot for ResaleNo reproduction or networking

44、permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89743 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 NOTES: 1. CL = 50 pF (includes test jig and probe capacitance). 2. Input signal from pulse generator: VIN = 0.0 V to 3

45、.0 V; PRR 1 MHz; ZOUT = 50 ; tr = 6.0 ns; tf = 6.0 ns; tr and tf shall be measured from 0.3 V to 2.7 V and from 2.7 V to 0.3 V, respectively; duty cycle = 50 percent. 3. The outputs are measured one at a time with one transition per measurement. FIGURE 4. Test circuit and switching waveforms - Conti

46、nued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89743 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 10 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Samplin

47、g and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in

48、 test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test