DLA SMD-5962-88678 REV B-2005 MICROCIRCUIT MEMORY DIGITAL CMOS UV ERASABLE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON《硅单片紫外线擦除可编程逻辑阵列互补型金属氧化物半导体数字存储微电路》.pdf

《DLA SMD-5962-88678 REV B-2005 MICROCIRCUIT MEMORY DIGITAL CMOS UV ERASABLE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON《硅单片紫外线擦除可编程逻辑阵列互补型金属氧化物半导体数字存储微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-88678 REV B-2005 MICROCIRCUIT MEMORY DIGITAL CMOS UV ERASABLE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON《硅单片紫外线擦除可编程逻辑阵列互补型金属氧化物半导体数字存储微电路》.pdf（14页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Change to the data retention stress/margin test. Editorial changes throughout. 89-12-13 M. A. Frye B Boilerplate update, part of 5 year review. ksr 05-11-15 Raymond Monnin THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV SH

2、ET REV STATUS REV B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY D. A. DiCenzo COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL APPRO

3、VED BY Michael A. Frye DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 88-09-26 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, UV ERASABLE, PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-88678 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5

4、962-E047-06 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88678 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing descr

5、ibes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN shall be as shown in the following example: 5962- 88678 01 R A | | | | | | | | | | | | Drawing number Device ty

6、pe Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number Circuit function tPD01, 05, 09 C16L8 16-input, 8-output, AND-OR inverted logic array 40, 30, 20 ns 02, 06, 10 C16R8 16-i

7、nput, 8-output, registered, AND-OR logic array 40, 30, 20 ns 03, 07, 11 C16R6 16-input, 6-output, registered, AND-OR logic array 40, 30, 20 ns 04, 08, 12 C16R4 16-input, 4-output, registered, AND-OR logic array 40, 30, 20 ns 1.2.2 Case outline(s). The case outline(s) shall be as designated in MIL-ST

8、D-1835, and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 dual-in-line package 1/ S GDFP2-F20 or CDFP3-F20 20 flat package 1/ X CQCC2-N20 20 square leadless chip carrier package 1/ 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-3

9、8535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range - -0.5 V dc to +7.0 V dc DC voltage applied to outputs in high Z - -0.5 V dc to +7.0 V dc DC input voltage - -3.0 V dc to +7.0 V dc Output sink current- 24 mA Thermal resistance, junction-to-case (JC): Cases R, S, and X- See MIL-ST

10、D-1835 Maximum power dissipation (PD) 2- 1.0 W Maximum junction temperature (TJ)- +175C Lead temperature (soldering, 10 seconds maximum) - +260C Storage temperature range - -65C to +150C Temperature under bias range- -55C to +125C 1.4 Recommended operating conditions. Supply voltage range (VCC)- +4.

11、5 V dc to +5.5 V dc High level input voltage range (VIH)- 2.0 V dc minimum Low level input voltage range (VIL) - 0.8 V dc maximum Case operating temperature range (TC) - -55C to +125C 1/ Lid shall be transparent to permit ultraviolet light erasure. 2/ Must withstand the added PDdue to short circuit

12、test (e.g., IOS). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88678 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Gove

13、rnment specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICA

14、TION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard

15、Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

16、 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMEN

17、TS 3.1 Item requirements The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or

18、a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) pla

19、n may make modifications to the requirements herein. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The d

20、esign, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.2 Truth table (unprogrammed devices). The truth table for unprogrammed devices shall be as specified

21、 on figure 2. 3.2.2.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in groups A, B, or C (see 4.3), the devices shall be programmed by the manufacturer prior to test with a minimum of 50

22、 percent of the total number of gates programmed or to any altered item drawing pattern which includes at least 25 percent of the total number of gates programmed. 3.2.2.2 Programmed devices. The truth tables for programmed devices shall be as specified by an attached altered item drawing. 3.2.3 Cas

23、e outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical

24、 test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5

25、962-88678 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ Device Group A Limits Unit -55C TC +125C type sub- 4.5 V VCC 5.5 V groups Min Max unless otherwise specified Ou

26、tput high voltage VOHVCC= 4.5 V, IOH= -2.0 mA, All 1,2,3 2.4 V VIN= VIHor VIL Output low voltage VOLVCC= 4.5 V, IOL= 12 mA, All 1,2,3 0.4 V VIN= VIHor VIL Input high voltage 2/ VIH All 1,2,3 2.0 V Input low voltage 2/ VIL All 1,2,3 0.8 V Input leakage current IIX VIN= 5.5 V to GND All 1,2,3 -10 10 A

27、 Output leakage current IOZVCC= 5.5 V All 1,2,3 -100 + 100 A VOUT= 5.5 V and GND Output short circuit IOSVCC= 5.5 V, VOUT= 0.5 V All 1,2,3 -300 mA current 3/ 4/ Power supply current ICCVCC= 5.5 V, IOUT= 0 mA All 1,2,3 70 mA 5/ VIN= GND | Input capacitance 4/ CIN f = 1.0 Mhz | VIN= 0.0 V 7 pF TA= +25

28、C | All 4 VCC= 5.0V | Output capacitance 4/ COUT(see 4.3.1c) | VOUT= 0.0 V 7 pF | Input or feedback to tPD 01,03,04 9,10,11 40 ns non-registered output VCC= 5.5V 05,07,08 30 see figures 3 and 4 09,11,12 20 Input to output enable tEA 01,03,04 9,10,11 40 ns 05,07,08 30 09,11,12 20 Input to output disa

29、ble tER 01,03,04 9,10,11 40 ns 4/ 6/ 05,07,08 30 09,11,12 20 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88678 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVIS

30、ION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions Device Group A Limits Unit -55C TC +125C type sub- 4.5 V VCC 5.5 V groups Min Max unless otherwise specified OE to output enabled tPZXVCC= 5.5V 02,03,04 9,10,11 25 ns see fig

31、ures 3 and 4 06,07,08 10,11,12 20 OE to output disabled tPXZ 02,03,04 9,10,11 25 ns 4/ 6/ 06,07,08 10,11,12 20 Clock to output tCO 02,03,04 9,10,11 25 ns 7/ 06,07,08 20 10,11,12 15 Input or feedback setup tS 02,03,04 9,10,11 35 ns time 7/ 06,07,08 25 10,11,12 20 Hold time 7/ tH 02,03,04 9,10,11 0 ns

32、 06,07,08 10,11,12 Clock period 4/ 7/ tP 02,03,04 9,10,11 60 ns 06,07,08 45 10,11,12 35 Clock width 4/ 7/ tW 02,03,04 9,10,11 25 ns 06,07,08 20 10,11,12 12 Maximum frequency fMAX 02,03,04 9,10,11 16.5 MHz 4/ 7/ 06,07,08 22 10,11,12 28.5 1/ AC test are performed with input rise and fall times of 5 ns

33、 or less, timing reference levels of 1.5 V, input pulse levels of 0 V to 3.0 V, and the output load on figure 3, configuration A. 2/ These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 3/ For test purposes, not more than one output a

34、t a time should be shorted. Short circuit test duration should not exceed 1 second. 4/ Tested initially and after any design or process changes that affect that parameter, and therefore shall be guaranteed to the limits specified in table I. 5/ To calculate ICCat any given operating frequency, use 7

35、0 mA + ICC(ac), where ICC(ac) = (0.6 mA/MHz) X (operating frequency in MHz). 6/ Transition is measured at steady state high level -500 mV or steady state low level +500 mV on the output from the 1.5 V level on the input and the output load on figure 3, configuration B. 7/ Test applies only to regist

36、ered outputs. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88678 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 Device types 01, 05, 09 02, 06, 10 0

37、3, 07, 11 04, 08, 12 Case outlines R, S, X R, S, X R, S, X R, S, X Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 I0I1I2 I3I4I5I6I7I8VSSI9O0I/O1I/O2I/O3I/O4I/O5I/O6O7VCCCP I0I1I2 I3I4I5I6I7VSSOE O0O1O2O3O4O5O6O7VCCCP I0I1I2 I3I4I5I6I7VSSOE I/O0O1O2O3O4O5O6I/O7VCCC

38、P I0I1I2 I3I4I5I6I7VSSOE I/O0I/O1O2O3O4O5I/O6I/O7VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88678 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVE

39、L B SHEET 7 DSCC FORM 2234 APR 97 Device types 01, 05, and 09 Truth table Input pins Output pins I9I8I7I6I5I4I3I2I1I0O7I/O6I/O5I/O4I/O3I/O2I/O1O0X X X X X X X X X X Z Z Z Z Z Z Z Z Device types 02, 06, and 10 Truth table Input pins Output pins CP OE I7I6I5I4I3I2I1I0O7O6O5O4O3O2O1O0X H X X X X X X X

40、X Z Z Z Z Z Z Z Z X L X X X X X X X X H H H H H H H H Device types 03, 07, and 11 Truth table Input pins Output pins CP OE I7I6I5I4I3I2I1I0I/O7O6O5O4O3O2O1I/O0X H X X X X X X X X Z Z Z Z Z Z Z Z X L X X X X X X X X Z H H H H H H Z Device types 04, 08, and 12 Truth table Input pins Output pins CP OE

41、I7I6I5I4I3I2I1I0I/O7I/O6O5O4O3O2I/O1I/O0X H X X X X X X X X Z Z Z Z Z Z Z Z X L X X X X X X X X Z Z H H H H Z Z NOTES: 1. Z = Three-state 2. X = Dont care FIGURE 2. Truth table (unprogrammed). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD

42、MICROCIRCUIT DRAWING SIZE A 5962-88678 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 FIGURE 3. Output load circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88678 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 FIGURE 4. Switching waveforms. Provided by IHSNot for ResaleNo reproductio