DLA SMD-5962-88676 REV A-2011 MICROCIRCUITS MEMORY DIGITAL CMOS 2K X 8 EEPROM MONOLITHIC SILICON.pdf

《DLA SMD-5962-88676 REV A-2011 MICROCIRCUITS MEMORY DIGITAL CMOS 2K X 8 EEPROM MONOLITHIC SILICON.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-88676 REV A-2011 MICROCIRCUITS MEMORY DIGITAL CMOS 2K X 8 EEPROM MONOLITHIC SILICON.pdf（18页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update body of drawing to reflect current requirements. glg 11-04-01 Charles Saffle THE ORIGINAL FIRST PAGE OF THE DRAWING HAS BEEN REPLACED. REV SHEET REV A A A SHEET 15 16 17 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5

2、6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS 2K

3、X 8 EEPROM, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 89-02-13 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-88676 SHEET 1 OF 17 DSCC FORM 2233 APR 97 5962-E277-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr

4、om IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88676 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with M

5、IL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN shall be as shown in the following example: 5962-88676 01 L X Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) shall identify the circuit f

6、unction as follows: Generic Access Write Write End of write Device type number Circuit function time speed mode indicator Endurance _ 01 (see 6.4) (2K X 8 EEPROM) 90 ns 1.0 ms byte DATA polling 10,000 cycles 02 70 ns 1.0 ms byte DATA polling 10,000 cycles 03 55 ns 1.0 ms byte DATA polling 10,000 cyc

7、les 1.2.2 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style J GDIP1-T24 or CDIP2-T24 24 Dual-in-line package L GDIP3-T24 or CDIP4-T24 24 Dual-in-line package X CQCC1-N32 32 Rectangular chip carrie

8、r package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.3 V dc to +6.25 V dc Storage temperature range . -65C to +150C Maximum power dissipation (PD) 1.0 W Lead temperature (soldering, 10 seconds) . +

9、300C Junction temperature (TJ) 2/ +175C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Input voltage range (VIL, VIH) -0.3 V dc to +6.25 V dc Data retention . 10 years (minimum) Endurance: . 10,000 cycles/byte (minimum) Chip clear voltage (VH) . 12.0 V dc 1.4 Recommended operating cond

10、itions. 1/ Supply voltage range (VCC) . +4.5 V dc to +5.5 V dc Case operating temperature range (TC) -55C to +125C Input voltage, low range (VIL) -0.1 V dc to +0.8 V dc Input voltage, high range (VIH) +2.0 V dc to VCC+0.3 V dc 1/ All voltages are referenced to VSS(ground). 2/ Maximum junction temper

11、ature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88676 DLA LAND AND M

12、ARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specifie

13、d, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interf

14、ace Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardizatio

15、n Document Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicab

16、le laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produc

17、ed by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordan

18、ce with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certif

19、ication mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The

20、terminal connections shall be as specified on figure 1. 3.2.2 Truth table. The truth table shall be as specified on figure 2. 3.2.2.1 Unprogrammed or erased devices. The truth table for programmed devices shall be as specified on figure 2. 3.2.2.2 Programmed devices. The requirements for supplying p

21、rogrammed devices are not part of this drawing. 3.2.3 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply o

22、ver the full case operating temperature range. 3.4 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not

23、 feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.4.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be

24、 replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88676 DLA LAND AND MARITIME COLU

25、MBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ Group A Device Limits Unit -55C TC+125C subgroups type VSS= 0 V, 4.5 V VCC 5.5 V unless otherwise specified Min Max Supply current ICC1CE = OE = VIL, WE = V

26、IH, 1,2,3 All 80 mA (operating) all I/Os = 0.0 mA, inputs = 5.5 V f = 1/ tAVAV(min) Supply current ICC2CE = VIH, OE = VIL, 1,2,3 All 3.0 mA (TTL standby) all I/Os = 0.0 mA, inputs = VCC -0.3 V, f = 0.0 MHz Supply current ICC3CE = VCC-0.3 V, 1,2,3 All 100 A (CMOS standby) all I/Os = 0.0 mA, Inputs =

27、VILor VCC-0.3 V, f = 0.0 MHz Input leakage IIHVIN= 5.5 V 1,2,3 All +10 A (high) Input leakage IILVIN= 0.1 V 1,2,3 All -10 A (low) Output leakage IOHZVOUT= 5.5 V, CE = VIH2/ 1,2,3 All +10 A (high) Output leakage IOLZVOUT= 0.1 V, CE = VIH2/ 1,2,3 All -10 A (low) Input voltage VIL 1,2,3 All -0.1 0.8 V

28、low Input voltage VIH 1,2,3 All 2.0 VCC+0.3 V high Output voltage VOLIOL= 12 mA, VIH= 2.0 V 1,2,3 All 0.45 V low VCC= 4.5 V, VIL= 0.8 V Output voltage VOHIOH= -4.0 mA, VIH= 2.0 V 1,2,3 All 2.4 V high VCC= 4.5 V, VIL= 0.8 V OE high leakage IOEVH= 13 V 1,2,3 All -10 100 A (chip erase) See footnotes at

29、 end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88676 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characterist

30、ics - Continued. Test Symbol Conditions 1/ Group A Device Limits Unit -55C TC+125C subgroups type VSS= 0 V, 4.5 V VCC 5.5 V unless otherwise specified Min Max Input CIVI= 0 V, VCC= 5.0 V 4 All 6.0 pF capacitance TA= +25C, f = 1 MHz 3/ 4/ See 4.3.1c Output COVO= 0 V, VCC= 5.0 V 4 All 12 pF capacitanc

31、e TA= +25C, f = 1.0 MHz 3/ 4/ See 4.3.1c Read cycle time 4/ tAVAVSee figure 3 5/ 9,10,11 01 90 ns 02 70 03 55 Address access tAVQV 9,10,11 01 90 ns time 02 70 03 55 Chip enable tELQV 9,10,11 01 90 ns access time 02 70 03 55 Output enable tOLQV 9,10,11 01 50 ns access time 02 50 03 40 Chip enable to

32、4/ tELQX 9,10,11 All 0 ns output in low Z See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88676 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FOR

33、M 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ Group A Device Limits Unit -55C TC+125C subgroups type VSS= 0 V, 4.5 V VCC 5.5 V unless otherwise specified Min Max Chip disable to 4/ tEHQZ See figure 3 5/ 9,10,11 01 50 ns output in high Z 02 50 03

34、 40 Output enable to 4/ tOLQX 9,10,11 All 0 ns output in low Z Output disable 4/ tOHQZ 9,10,11 01 50 ns to output in high Z 02 50 03 40 Output hold from tAXQX 9,10,11 All 0 ns address change Write cycle time tWHWL See figures 4 and 5 5/ 9,10,11 All 1.0 ms tEHEL1 as applicable Address setup time tAVE

35、L 9,10,11 All 0 ns tAVWL Address hold time tELAX 9,10,11 All 5.0 ns tWLAX Write setup time tWLEL 9,10,11 All 0 ns tELWL Write hold time tEHWH 9,10,11 All 0 ns tWHEH OE setup time tOHEL 9,10,11 All 0 ns tOHWL OE hold time tEHOL 9,10,11 All 0 ns tWHOL WE pulse width tELEH 9,10,11 All 100 ns tWLWH1 See

36、 footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88676 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance

37、 characteristics - Continued. Test Symbol Conditions 1/ Group A Device Limits Unit -55C TC+125C subgroups type VSS= 0 V, 4.5 V VCC 5.5 V unless otherwise specified Data setup time tDVEH See figures 4 and 5 5/ 9,10,11 All 50 ns tDVWH as applicable Delay to next write 4/ tDVWL 9,10,11 All 0 s tDVEL Da

38、ta hold time tEHDX 9,10,11 All 0 ns tWHDX Last byte loaded 4/ tWHEL 9,10,11 All 0 ns to data polling tEHEL CE setup time tELWL1See figure 6 5/ 9,10,11 All 5.0 s Output setup time tOVHWL 9,10,11 All 5.0 s CE hold time tWHEH1 9,10,11 All 5.0 s OE hold time tWHOH 9,10,11 All 5.0 s High voltage VH 9,10,

39、11 All 12 13 V Chip erase time tWLWH2 9,10,11 All 10 210 ms 1/ DC and read mode. 2/ Connect all address inputs and to VIHand measure IOLZand IOHZwith the output under test connected to VOUT. 3/ All pins not being tested are to be open. 4/ Tested initially and after any design or process changes that affect that parameter, and therefore guaranteed to the limits specified in table I. 5/ Tested by application of specified timing signals and conditio