DLA SMD-5962-88659 REV C-2013 MICROCIRCUIT LINEAR 12-BIT VOLTAGE OUTPUT D A CONVERTER MICROPROCESSOR COMPATIBLE MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add case outline 3. Change conditions for Supply Current test IEE. Editorial changes throughout. 92-01-17 M. A. Frye B Update to current requirements. Editorial changes throughout. drw 02-02-25 Raymond Monnin C Redrawn. Update paragraphs to MIL-P

2、RF-38535 requirements. - drw 13-12-02 Charles F. Saffle THE FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV SHEET REV STATUS REV C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Joseph A. Kerby DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/

3、www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Charles E. Besore APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, 12-BIT VOLTAGE OUTPUT D/A CONVERTER, MICROPROCESSOR COMPATIBLE, MONO

4、LITHIC SILICON DRAWING APPROVAL DATE 88-08-30 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-88659 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E069-14 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88659

5、 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (

6、PIN). The complete PIN is as shown in the following example: 5962-88659 01 X A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type. The device type identifies the circuit function as follows: Device type Generic number Circuit function 01 AD667 D

7、/A converter, 12-bit, voltage output, microprocessor compatible 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T28 or CDIP2-T28 28 dual-in-line 3 CQCC1-N28 28 square leadless chip carrier 1.2.

8、3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. VCCto power ground range 0 V dc to +18 V dc VEEto power ground range 0 V dc to -18 V dc Digital inputs (pins 11-15, 17-28) to power ground range -1.0 V dc to 7.0 V dc Reference in to reference

9、ground 12 V dc Bipolar offset to reference ground 12 V dc 10 V span R to reference ground . 12 V dc 20 V span R to reference ground . 24 V dc Reference out, VOUT(pins 6 and 9) continuous short to power ground, momentary short to VCCPower dissipation (PD) . 1,000 mW 1/ Storage temperature range -65C

10、to +150C Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Thermal resistance, junction-to-ambient (JA): Case outline X 60C/W Case outline 3 125C/W 1.4 Recommended operating conditions. Supply voltage range (VCC) +11.4 V dc to +16.5 V dc Supp

11、ly voltage range (VEE) -11.4 V dc to -16.5 V dc Ambient operating temperature range (TA) -55C to +125C 1/ Must withstand the added PDdue to short circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING S

12、IZE A 5962-88659 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified he

13、rein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Micro

14、circuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil or from t

15、he Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, s

16、upersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this draw

17、ing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity ap

18、proval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “

19、Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case out

20、lines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Block diagram. The block diagram shall be as specified on figure 2. 3.2.4 Truth table. The truth table shall be as specified on figure 3. 3

21、.2.5 Timing diagram. The timing diagram shall be as specified on figure 4. 3.2.6 Test circuit for 20 V FSR. The test circuit for 20 V FSR shall be as specified on figure 5. 3.2.7 Test circuit for 10 V FSR. The test circuit for 10 V FSR shall be as specified on figure 6. Provided by IHSNot for Resale

22、No reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88659 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless otherwise specified herein, the elect

23、rical performance characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in ta

24、ble I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the

25、manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certificat

26、ion mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of complian

27、ce submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-

28、38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and M

29、aritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without

30、license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88659 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups De

31、vice type Limits Unit Min Max Resolution RES All 12 Bits Integral linearity error LE 2/ 1 All -0.5 +0.5 LSB 2, 3 -0.75 +0.75 Differential linearity error DLE 3/ 1 All -0.75 +0.75 LSB 2, 3 -1 +1 Gain error AEAll bits high 1 All -0.2 +0.2 % of FSR Gain drift 4/ AE/T 2, 3 -30 +30 ppm of FSR/C Unipolar

32、offset error VOSAll bits low 1 All -2 +2 LSB Unipolar offset drift 4/ VOS/T 2, 3 -3 +3 ppm of FSR/C Bipolar zero error 5/ BPZEMSB high, all other bits low 1 All -0.1 +0.1 % of FSR Bipolar zero drift 4/, 5/ BPZE/T 2, 3 -10 +10 ppm of FSR/C Reference voltage VREFVCC= +11.4 V, VEE= -11.4 V 6/ 1, 2, 3 A

33、ll 9.9 10.1 V Latch functionality VOS 7/ 1, 2, 3 All -1 +1 LSB AE7/, 8/ -1 +1 Output current IOUTTA= +25C 9/ 1 All -5 +5 mA Output short circuit current IOSTA= +25C 9/ 1 All 40 mA Power supply rejection ratio PSSR+ +11.4V VCC +16.5 V, All bits high, TA= +25C 1 All -10 +10 ppm of FS/% PSSR- -16.5V VE

34、E -11.4 V, All bits high, TA= +25C -10 +10 Power supply current ICCVCC= +16.5 V, VEE= -16.5 V All bits high 1 All 12 mA IEETA= +25C All bits low -25 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT

35、DRAWING SIZE A 5962-88659 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max D

36、igital input high voltage VIHTA= +25C 1 All 2.0 V Digital input low voltage VIL1 All 0.8 V 2, 3 0.7 Digital input high current IIHTA= +25C, VIH= 5.5 V 1 All 10 A Digital input low current IILTA= +25C, VIL= 0 V 1 All 5 A Functional tests See 4.3.1c 7, 8 All Output voltage settling time tSLRL= 2k, 9/

37、CL= 500 pF, See figure 5 20 V FSR 9 All 4 s TA= +25C, See figure 4 See figure 6 10 V FSR 3 CS pulse width tCPTA= +25C, See figure 4, 9/ 9 All 100 ns Data setup time tDCTA= +25C, See figure 4, 9/ 9 All 50 ns Data hold time tDHTA= +25C, See figure 4, 9/ 9 All 0 ns Address valid to end of CS tACTA= +25

38、C, See figure 4, 9/ 9 All 100 ns 1/ VCC= +15 V dc, VEE= -15 V dc, CS , A0, A1, A2, A3 = logic “0”, VIH=2.0 V, VIL= 0.8 V, 50 resistor pin 6 to pin 7. Unipolar configuration (pins 1 and 2 to pin 9, pin 4 to pin 5, unless otherwise specified). 2/ All bits with positive errors on. All bits with negativ

39、e errors on. 3/ Major carry transitions. 4/ VOS/t, AE/t, BPZE/t are determined for measurements made at +125C, +25C, and -55C for VOS, AE, and BPZErespectively. Drift is specified from +25C to +125C and from +25C to -55C. 5/ Bipolar configuration (pins 1 to 9, 50 resistor pin 4 to pin 6). 6/ In subg

40、roup 1, the reference output is loaded with 0.5 mA nominal reference current, 1.0 mA bipolar offset current and 0.1 mA additional current. In subgroups 2 and 3, only the 0.5 mA reference input current is applied. The reference must be buffered to supply external loads at elevated temperatures. 7/ Al

41、l bits low, A0, A1, A2, A3 are logic “0”; A0, A1, A2, A3 are initialized to logic “1”, each 4-bit register set to logic “1”, and A0, A1, A2 are set sequentially to logic “0” and back to logic “1” to latch data into first rank. 8/ A3 is set to logic “0” and back to logic “1” to latch full scale outpu

42、t into second rank. 9/ Guaranteed, if not tested, to the limits specified. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88659 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC F

43、ORM 2234 APR 97 Device type 01 Case outline X and 3 Terminal number Terminal symbol 1 20 V SPAN 2 10 V span 3 SUM JCT 4 BIP OFF 5 AGND 6 VREFOUT 7 VREFIN 8 VCC9 VOUT10 VEE11 CS 12 A3 13 A2 14 A1 15 A0 16 POWER GND 17 DB0 (LSB) 18 DB1 19 DB2 20 DB3 21 DB4 22 DB5 23 DB6 24 DB7 25 DB8 26 DB9 27 DB10 28

44、 DB11 (MSB) FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88659 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 FIGURE 2. Block

45、 diagram. CS A3 A2 A1 A0 Operation 1 X X X X No operation X 1 1 1 1 No operation 0 1 1 1 0 Enable 4 LSBs of first rank 0 1 1 0 1 Enable 4 middle bits of first rank 0 1 0 1 1 Enable 4 MSBs of first rank 0 0 1 1 1 Loads second rank from first rank 0 0 0 0 0 All latches transparent “X” = Dont care. FIG

46、URE 3. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88659 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 9 DSCC FORM 2234 APR 97 FIGURE 4. Timing waveforms. Provided by

47、 IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88659 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 10 DSCC FORM 2234 APR 97 NOTE: 10 V bipolar voltage output. FIGURE 5. Test circuit for 20 V FS

48、R. NOTE: 0 V to +10 V unipolar voltage output. FIGURE 6. Test circuit for 10 V FSR. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88659 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 11 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be