DLA SMD-5962-88637 REV D-2010 MICROCIRCUIT MEMORY DIGITAL CMOS FIELD PROGRAMMABLE GATE ARRAY MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R005-91. 91-09-24 M. A. Frye B Changed the minimum clock period for device 02 from 45 to 40 ns. Boilerplate update. ksr 99-07-28 Raymond Monnin C Boilerplate update, part of 5 year review. ksr 05-09-29 Raymond

2、Monnin D Boilerplate update, part of 5 year review. ksr 10-11-10 Charles F. Saffle REV SHET REV SHET REV STATUS REV D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Rick Officer DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Raymond Monnin COLUM

3、BUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL APPROVED BY D. A. DiCenzo MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, MONOLITHIC SILICON DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 88-07-28 AMSC N/A REVISION

4、 LEVEL D SIZE A CAGE CODE 67268 5962-88637 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E051-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88637 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL

5、 D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN shall be as shown in the following examp

6、le: 5962- 88637 01 L A | | | | | | | | | | | | Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number Circuit function tPD01 20G10 24 Pin Generic CMOS

7、PLD 40 ns 02 20G10 24 Pin Generic CMOS PLD 30 ns 1.2.2 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835, and as follows: Outline letter Descriptive designator Terminals Package style K GDFP2-F24 or CDFP3-F24 24 flat package L GDIP3-T24 or CDIP4-T24 24 dual-in-line package

8、3 CQCC1-N28 28 square leadless chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range - -0.5 V dc to +7.0 V dc DC voltage applied to Outputs in High Z state range - -0.5 V dc to +7.0 V dc DC Input volta

9、ge - -3.0 V dc to +7.0 V dc DC program voltage - +14.0 V dc Maximum power dissipation 1/ - 1.0 W Lead temperature (soldering, 10 seconds) - +260C Thermal resistance, junction-to-case (JC): - See MIL-STD-1835 Junction temperature (TJ) 2/ - +150C Storage temperature range - -65C to +150C Temperature u

10、nder bias range - -55C to +125C 1.4 Recommended operating conditions. Supply voltage range (VCC) - +4.5 V dc to +5.5 V dc Ground voltage (GND) - 0 V dc High level input voltage range (VIH) - 2.0 V dc to VCCLow level input voltage range (VIL) - -0.5 V dc to +0.8 V dc Case operating temperature range

11、(TC) - -55C to +125C 1/ Must withstand the added PDdue to short circuit test (e.g., IOS). 2/ Maximum junction temperature may be increased to 175C during burn-in and steady state life. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIR

12、CUIT DRAWING SIZE A 5962-88637 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the exten

13、t specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method

14、Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dl

15、a.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing

16、in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein.

17、 Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan

18、 and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance wit

19、h MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance

20、with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table (unprogrammed devices). The truth table for unprogrammed devices shall be as specified on figure 2. 3.2.4 Programmed devices. The truth table for programmed devices shall be s

21、pecified by an altered item drawing. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical

22、test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN

23、may also be marked. For packages where the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535

24、, Appendix A. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88637 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3.6 Certificate of compliance. A certificate

25、of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply shall affirm that the manufacturers product

26、 meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification

27、 of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritime s agent and the acquiring activity retain the option to review the manufacturers facility and applicable required documentatio

28、n. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-

29、883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test (method 1015 of MIL-STD-883). (1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control a

30、nd shall be made available to the preparing or procuring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electr

31、ical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 incl

32、uding groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CINand COUTmeasurement) shall be measured

33、only for the initial test and after process or design changes which may affect input capacitance. d. For unprogrammed devices, a sample shall be selected to satisfy programmability requirements prior to performing subgroups 9, 10, and 11. Twelve devices shall be submitted to programming (see 4.4). I

34、f more than two devices fail to program, the lot shall be rejected. At the manufacturers option, the sample may be increased to 24 total devices with no more than 4 total device failures allowed. e. For unprogrammed devices, 10 devices from the programmability sample shall be submitted to the requir

35、ements of group A, subgroups 9, 10, and 11. If more than two devices fail, the lot shall be rejected. At the manufacturers option, the sample may be increased to 20 total devices with no more than 4 total device failures allowable. f. Subgroups 7 and 8 shall consist of verifying the pattern specifie

36、d. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88637 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Sy

37、mbol Conditions Device Group A Limits Unit -55C TC +125C type sub- 4.5 V VCC 5.5 V groups Min Max unless otherwise specified Output high voltage VOHVCC= 4.5 V, IOH= -2.0 mA, All 1,2,3 2.4 V VIN= VIHor VIL Output low voltage VOLVCC= 4.5 V, IOL= 12 mA, All 1,2,3 0.5 V VIN= VIHor VIL Input high voltage

38、 1/ VIH All 1,2,3 2.0 V Input low voltage 1/ VIL All 1,2,3 0.8 V Input current IIX VIN= 5.5 V to GND All 1,2,3 -10 10 A Output leakage current IOZVCC= 5.5 V All 1,2,3 -100 + 100 A VOUT= 5.5 V and GND Output short circuit IOSVCC= 5.5 V, VOUT= 0.5 V All 1,2,3 -90 mA current 2/ 3/ Power supply current

39、ICCVCC= 5.5 V, IOUT= 0 mA All 1,2,3 80 mA VIN= 2.0 V | Input capacitance CIN f = 1.0 Mhz | VIN= 0.0 V 10 pF TA= +25C | All 4 VCC= 5.0V | Output capacitance COUT(see 4.3.1c) | VOUT= 0.0 V 10 pF | Functional tests See 4.3.1d All 7, 8 VIL= 0.0 V, VIH= 3.0 V Input or feedback to tPD 01 9,10,11 40 ns non

40、-registered output 4/ 02 30 Input to output enable tEA 01 9,10,11 40 ns 3/ 4/ 02 30 See footnotes at end of table.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88637 DLA LAND AND MARITIME COLUMBUS, OHIO 432

41、18-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions Device Group A Limits Unit -55C TC +125C type sub- 4.5 V VCC 5.5 V groups Min Max unless otherwise specified Input to output disable tER 01 9,10,11 40 ns 3/ 5/ 0

42、2 30 OE to output enabled tPZX All 9,10,11 25 ns 5/ OE to output disabled tPXZ All 9,10,11 25 ns 3/ 5/ Clock to output tCO 01 9,10,11 25 ns 4/ 02 20 Input or feedback setup tS 01 9,10,11 35 ns time 4/ 02 20 Hold time 4/ tH All 9,10,11 0 ns Clock period 3/ 4/ tP 01 9,10,11 60 ns 02 40 Clock width 3/ 4/ tW 01 9,10,11 25 ns 02 20 Maximum frequency fMAX 01 9,10,11 16.5 MHz 3/ 4/ 02 25 1/ These are absolute values with respect to device ground an