DLA SMD-5962-87600 REV A-2006 MICROCIRCUIT LINEAR 8-BIT A D CONVERTER MONOLITHIC SILICON《硅单块 8比特交直流转换器 直线型微型电路》.pdf

《DLA SMD-5962-87600 REV A-2006 MICROCIRCUIT LINEAR 8-BIT A D CONVERTER MONOLITHIC SILICON《硅单块 8比特交直流转换器 直线型微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-87600 REV A-2006 MICROCIRCUIT LINEAR 8-BIT A D CONVERTER MONOLITHIC SILICON《硅单块 8比特交直流转换器 直线型微型电路》.pdf（13页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements. Editorial changes throughout. - drw 06-10-02 Raymond Monnin REV SHET REV SHET REV STATUS REV A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Joseph A. Kerby DEFENSE S

2、UPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY D. A. DiCenzo COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, 8-BIT A/D CONVERTER, AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING

3、APPROVAL DATE 87-12-08 MONOLITHIC SILICON AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-87600 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E666-06 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87600 DEF

4、ENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Num

5、ber (PIN). The complete PIN is as shown in the following example: 5962-87600 01 X A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type. The device type identifies the circuit function as follows: Device type Generic number Circuit function 01 TDC10

6、48 8-bit A/D converter 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T28 or CDIP2-T28 28 Dual-in-line 3 CQCC1-N28 28 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as spec

7、ified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. VCCto DGND-0.5 V dc to +7.0 V dc VEEto AGND+0.5 V dc to -7.0 V dc AGNDto DGND-0.5 V dc to +0.5 V dc CONV, NMINV, or NLINV to DGND. -0.5 V dc to +5.5 V dc VIN, VRT, or VRBto AGND+0.5 V dc to VEEVRTto VRB-2.2 V dc to +2.2 V dc Applied o

8、utput voltage to DGND-0.5 V dc to 5.5 V dc 1/ Applied output current, externally forced -1.0 mA to +6.0 mA 2/, 3/ Output short-circuit duration. 1.0 s 4/ Storage temperature range -65C to +150C Lead temperature (soldering, 10 seconds) +300C Power dissipation, worst case (PD) 2.1 W Thermal resistance

9、, junction-to-case (JC). See MIL-STD-1835 _ 1/ Applied voltage must be current limited to specified range. 2/ Forcing voltage must be limited to specified range. 3/ Current is specified as positive when flowing into the device. 4/ Single output in high state to ground. Provided by IHSNot for ResaleN

10、o reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87600 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Positive supply voltage (VCC) . 4.5 V dc t

11、o 5.5 V dc Negative supply voltage (VEE) -4.9 V dc to -5.5 V dc Analog ground voltage to DGND(VAGND) . -0.1 V dc to +0.1 V dc CONV pulse width, low (tPWL). 18 ns minimum CONV pulse width, high (tPWH). 22 ns minimum Input voltage, logic low (VIL). 0.8 V dc maximum Input voltage, logic high (VIH). 2.0

12、 V dc minimum Output current, logic low (IOL). 4.0 mA maximum Output current, logic high (IOH). -400 A maximum Most positive reference input (VRT) 5/ -0.1 V dc to +0.1 V dc Most negative reference input (VRB) 5/. -1.9 V dc to -2.1 V dc Voltage reference differential (VRT VRB) 1.8 V dc to 2.1 V dc In

13、put voltage (VIN) VRBto VRTCase operating temperature range (TC). -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified

14、, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interfa

15、ce Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil

16、 or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document,

17、however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 5/ VRTmust be more positive than VRB, and VRT VRBmust be within the specified range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCI

18、RCUIT DRAWING SIZE A 5962-87600 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and

19、as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers a

20、pproved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications sh

21、all not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-P

22、RF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Block diagram. The block diagram shall be as specified on figure 2. 3.2.4 Truth table. The t

23、ruth table shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The el

24、ectrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufactu

25、rers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devi

26、ces built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from

27、 a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A

28、and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any chang

29、e that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSN

30、ot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87600 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Condi

31、tions 1/ -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxPositive supply current, static ICCVEE= -4.9 V, VCC= 5.5 V 1, 2, 3 01 40 mA Negative supply current, static IEEVEE= -5.5 V 1, 2, 3 01 -320 mA Reference current IREFVEE= -4.9 V, VRT= 0 V, VRB= -2.0 V 1,

32、 2, 3 01 5.0 50 mA Total reference resistance 2/ RREFVRT= 0 V, VRB= -2.0 V 1, 2, 3 01 40 400 Input equivalent resistance 2/ RINVRT= 0 V, VRB= -2.0 V 1, 2, 3 01 10 4000 k Input capacitance 2/ CINVRT= 0 V, VRB= -2.0 V 4, 5, 6 01 100 pF Input constant bias current ICBVEE= -5.5 V, VCC= 5.5 V 1, 2, 3 01

33、550 A Input low current IILCONV 1, 2, 3 01 -400 A VEE= -4.9 V, VCC= 5.5 V, VI= 0.4 V NLINV, NMINV -600 Input high current IIHVEE= -4.9 V, VCC= 5.5 V, VI= 2.4 V 1, 2, 3 01 50 A Input current at maximum input voltage IIVEE= -4.9 V, VCC= 5.5 V, VI= 5.5 V 1, 2, 3 01 1.0 mA Output short-circuit current 3

34、/ IOSVEE= -4.9 V, VCC= 5.5 V 1, 2, 3 01 -30 mA Output low voltage VOLVEE= -5.5 V, VCC= 4.5 V, IOL= 4.0 mA 1, 2, 3 01 0.5 V Output high voltage VOHVCC= 4.5 V, IOH= -400 A 1, 2, 3 01 2.4 V Digital input capacitance 2/ CIf = 1.0 MHz 4 01 15 pF Maximum conversion rate FSVEE= -4.9 V, VCC= 4.5 V, FS= 20 M

35、Hz minimum per figure 4 4, 5, 6 01 20 MSPS 4/ Functional tests VEE= -4.9 V, VCC= 4.5 V, f = 1.0 MHz, see 4.3.1b 7, 8 01 Sampling time offset 2/ tSTOSee figure 4 9, 10, 11 01 0 15 ns Digital output delay tDVEE= -4.9 V, VCC= 5.5 V, see figure 4 9, 10, 11 01 5.0 35 ns Digital output hold time 2/ tHOSee

36、 figure 4 9, 10, 11 01 5.0 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87600 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2

37、234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxLinearity error integral, independent ELIVRT= 0 V, VRB= -2.0 V, FS= 100 kHz 4, 5, 6 01 0.2 % Linearity error, di

38、fferential ELDVRT= 0 V, VRB= -2.0 V, FS= 100 kHz 4, 5, 6 01 0.2 % Nominal code size Q FS= 100 kHz 01 25 175 % Offset error, top 2/ EOTVIN= midpoint of code 0 1, 2, 3 01 +50 mV Missing codes QMISSFS= 100 kHz 01 0 codes Offset error, bottom 2/ EOBVIN= midpoint of code 255 1, 2, 3 01 -30 mV Temperature

39、 coefficient of offset error 2/ EOT 1, 2, 3 01 50 V/C Bandwidth full power input 2/ BW 4, 5, 6 01 5.0 MHz Signal-to-noise ratio (20 MSPS conversion rate, SNR Peak signal/ RMS noise 1.248 MHz input 4, 5, 6 01 53 dB 10 MHz bandwidth) 2/ 2.438 MHz input 52 RMS signal/ RMS noise 1.248 MHz input 44 2.438

40、 MHz input 43 Differential phase error 2/ 5/ DP FS= 4 X NTSC 4, 5, 6 01 1.0 degree Differential gain error 2/ 5/ DG FS= 4 X NTSC 4, 5, 6 01 2.0 % 1/ Unless otherwise specified, characteristics apply over the recommended operating conditions specified in 1.4 herein. 2/ Guaranteed if not tested. 3/ Ou

41、tput high, one pin to ground, one second duration maximum. 4/ Mega samples per second. 5/ In excess of quantization. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87600 DEFENSE SUPPLY CENTER COLUMBUS COLUMB

42、US, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outlines X and 3 Terminal number Terminal symbol 1 D1(MSB) 2 D23 D34 D45 DGND6 VCC7 VEE8 VEE9 VEE10 VCC11 DGND12 NLINV 13 D514 D615 D716 D8(LSB) 17 CONV 18 RT19 AGND20 VIN21 VIN22 VIN23 VIN24 VIN25 AGND26 RB27 RM2

43、8 NMINV FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87600 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 FIGURE 2.

44、Block diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87600 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 9 DSCC FORM 2234 APR 97 Binary Offset twos complement Step

45、Range True Inverted True Inverted -2.0000 V FS-2.0480 V FSNMINV = 1 0 0 1 7.8431 mV Step 8.000 mV Step NLINV = 1 0 1 0 000 0.0000 V 0.0000 V 00000000 11111111 10000000 01111111 001 -0.0078 V -0.0080 V 00000001 11111110 10000001 01111110 127 -0.9961 V -1.0160 V 01111111 10000000 11111111 00000000 128

46、 -1.0039 V -1.0240 V 10000000 01111111 00000000 11111111 129 -1.0118 V -1.0320 V 10000001 01111110 00000001 11111110 254 -1.9921 V -2.0320 V 11111110 00000001 01111110 10000001 255 -2.0000 V -2.0400 V 11111111 00000000 01111111 10000000 NOTES: 1. MNINV and NLINV are to be considered dc controls. The

47、y may be tied to +5.0 V for logic “1” and tied to ground for logic “0”. 2. Voltages are code midpoints when calibrated by adjusting VRTand VRBto set the 1stand 255ththresholds to the desired voltages. Note that R1is greater than R (refer to block diagram on figure 2 herein), ensuring calibration wit

48、h a positive voltage on RT. Assuming a 0 V to -2.0 V desired range, continuously strobe the converter with -0.0039 V (1/2 LSB from 0 V) on the analog input, and adjust VRTfor output toggling between codes 00 and 01. Then apply -1.996 V (1/2 LSB from -2.0 V) and adjust VRBfor toggling between codes 254 and 255. The degree of required adjustment is indicated by the offset error, EOTand EOB. Offset errors are gen