DLA SMD-5962-87593 REV C-2006 MICROCIRCUITS MEMORY DIGITAL NMOS 256 X 8 BIT RAM MONOLITHIC SILICON《硅单块 256 X8比特随机存取存储器 N沟道金属氧化物半导体 数字主存储器微型电路》.pdf

《DLA SMD-5962-87593 REV C-2006 MICROCIRCUITS MEMORY DIGITAL NMOS 256 X 8 BIT RAM MONOLITHIC SILICON《硅单块 256 X8比特随机存取存储器 N沟道金属氧化物半导体 数字主存储器微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-87593 REV C-2006 MICROCIRCUITS MEMORY DIGITAL NMOS 256 X 8 BIT RAM MONOLITHIC SILICON《硅单块 256 X8比特随机存取存储器 N沟道金属氧化物半导体 数字主存储器微型电路》.pdf（17页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Delete one vendor, CAGE 34335. Made changes to table I, table II, figure 1, and throughout drawing. Added figure 8. Device 02QX is inactive for new design. 88-10-12 M. A. Frye B Updated boilerplate. Added provisions for the supply of QD certified parts to t

2、he drawing. Added CAGE 3V146 to drawing. - glg 00-09-19 Raymond Monnin C Boilerplate update, part of 5 year review. ksr 06-10-11 Raymond Monnin THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHEET C C REV 15 16 SHEET REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4

3、5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Rick Officer CHECKED BY D. A. DiCenzo DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil APPROVED BY N. A. Hauck MICROCIRCUITS, MEMORY, DIGITAL, NMOS, 256 x 8 BIT RAM, MONOLITHIC SILICON DRAWING APPROVAL DATE 07-August 1987 S

4、IZE A CAGE CODE 67268 5962-87593 STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A REVISION LEVEL C SHEET 1 OF 16 DSCC FORM 2233 APR 97 5962-E643-06 Provided by IHSNot for ResaleNo reproduction or networking permitte

5、d without license from IHS-,-,-SIZE A 5962-87593 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B micro

6、circuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN shall be as shown in the following example: 5962-87593 01 Q X | | | | | | | | | | | | Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device typ

7、e(s). The device type(s) shall identify the circuit function as follows: Device type Generic number Circuit function 01 8155 2K RAM W/ I/O ports and timer, IIL( CE ) 02 8156 2K RAM W/ I/O ports and timer, IIL(CE) 1.2.2 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835, and

8、as follows: Outline letter Descriptive designator Terminals Package style Q CDIP2-T40 or GDIP1-T40 40 dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage to ground potential . -0.5 V dc to +7.0 V dc DC input volta

9、ge with respect to GND -0.5 V dc to +7.0 V dc Maximum power dissipation (PD):. 1.5 W Lead temperature (soldering, 10 seconds) +270C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Storage temperature range -65C to +150C Junction temperature (TJ) . +150C 1.4 Recommended operating condition

10、s. Case operating temperature range (TC). -55C to +125C Input low voltage (VIL) 0.8 V dc Input high voltage (VIH) 2.0 V dc Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87593 STANDARD MI

11、CROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent s

12、pecified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Sta

13、ndard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mi

14、l/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing s

15、hall take precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B de

16、vices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manuf

17、acturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certif

18、ication mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. This drawing has been modified to allow the manufacturer to use the alternate die/fabrication requirements of paragraph A.3.2.2 of MIL-PRF-38535 or alternative approved by the Qualifying Activity.

19、 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.2 Case outlines. The case outlines shall be

20、 in accordance 1.2.2 herein. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test req

21、uirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also

22、 be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in comp

23、liance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-

24、SIZE A 5962-87593 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supp

25、ly in MIL-HDBK-103 or QML-38535 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of confor

26、mance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and revi

27、ew. DSCC, DSCCs agent and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection pr

28、ocedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test (method 1015

29、of MIL-STD-883). (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or procuring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as

30、 applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manuf

31、acturer. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein.

32、b. Subgroups 4, 5, and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroups 7 and 8 shall test sufficient to verify the functional operation of the device. 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-stat

33、e life test conditions, method 1005 of MIL-STD-883. (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or procuring activity upon request. The test circuit shall specify the inputs, outputs

34、, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. (2) TA= +125C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. Provided by IHSNot for ResaleNo reproduction or networking permitted witho

35、ut license from IHS-,-,-SIZE A 5962-87593 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. | | | | | Limits | Test |Symbol | Conditions | Group A | Device | | Unit |

36、| -55C TC +125C | subgroups | types | Min | Max | | | | | | | | | | | | | 1/ | | Input low voltage | VIL| VCC= 4.5 V | 1, 2, 3 | All |-0.5 | 0.8 | V | | | | | | | | | | | | | 1/ | Input high voltage | VIH| VCC= 4.5 V | 1, 2, 3 | All | 2.0 | VCC| V | | | | | | +0.5 | | | | | | | | Output low voltage

37、| VOL| VIL= 0.8 V, IOL= 2.0 mA | 1, 2, 3 | All | | 0.45 | V | | VCC= 5.5 V, VIH= 2.0 V | | | | | | | | | | | | | | | | | | | Output high voltage | VOH| VIL= 0.8 V, VIH= 2.0 V | 1, 2, 3 | All | 2.4 | | V | | VCC= 5.5 V, IOH= -400 A | | | | | | | | | | | | | | | | | | | Input leakage current | IIL| VC

38、C= 5.5 V, | 1, 2, 3 | All | | 10 | A | | VIN= 5.5 V to 0 V | | | | -10 | A | | | | | | | | | | | | | | Output leakage current | IOL| VCC= 5.5 V, | 1, 2, 3 | All | | 10 | A | | VOUT= 5.5 V to 0.45 V | | | | -10 | A | | | | | | | | | | | | | | VCCsupply current | ICC| VCC= 5.5 V 2/ | 1, 2, 3 | All | |

39、 125 | mA | | | | | | | | | | | | | | Chip enable leakage | IIL | VCC= 5.5 V | 1, 2, 3 | 01 | | 160 | A (CE) | | VIN= 5.5 V to 0 V | | | | | | | | | | | | | | | | | | | Chip enable leakage | IIL| VCC= 5.5 V | 1, 2, 3 | 02 | | 100 | A (CE) | | VIN= 5.5 V to 0 V | | | | | | | | | | | | | | | | | | | F

40、unctional testing | | See 4.3.1c | 7, 8 | | | | | | | | | | | See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87593 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVI

41、SION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. | | | | | Limits | Test |Symbol | Conditions | Group A | Device | | Unit | | -55C TC +125C | subgroups | types | Min | Max | | | | | | | | | | | | | | | Address to LATCH setup | tAL| VCC= 5.5 V, 4

42、.5 V |9, 10, 11 | All | 50 | | ns time | | | | | | | | | VIH= 2.4 V | | | | | Address hold time | tLA| |9, 10, 11 | All | 80 | | ns after LATCH | | VIL= 0.45 V | | | | | | | | | | | | LATCH to READ/WRITE | tLC| VOH= 2.0 V |9, 10, 11 | All |100 | | ns control | | | | | | | | | VOL= 0.8 V | | | | | Va

43、lid data out from | tRD| |9, 10, 11 | All | | 170 | ns READ control | | | | | | | | | | | | | | Address stable to data | tAD| |9, 10, 11 | All | | 400 | ns out valid | | | | | | | | | | | | | | LATCH enable width | tLL| |9, 10, 11 | All |100 | | ns | | | | | | | | | | | | | | Data bus float after |

44、tRDF| |9, 10, 11 | All | 0 | 100 | ns READ 3/ | | | | | | | | | | | | | | READ/WRITE control to | tCL| |9, 10, 11 | All | 20 | | ns LATCH enable | | | | | | | | | | | | | | READ/WRITE control | tCC| |9, 10, 11 | All |250 | | ns width | | | | | | | | | | | | | | Data into WRITE | tDW| 4/ |9, 10, 11 |

45、 All |150 | | ns setup time | | | | | | | | | | | | | | Data in hold time | tWD| |9, 10, 11 | All | 25 | | ns after WRITE | | | | | | | | | | | | | | Recovery time between | tRV| |9, 10, 11 | All |300 | | ns controls | | | | | | | | | | | | | | WRITE to port output | tWP| |9, 10, 11 | All | | 400 |

46、ns | | | | | | | | | | | | | | Port input setup time | tPR| |9, 10, 11 | All | 70 | | ns | | | | | | | | | | | | | | Port input hold time | tRP| |9, 10, 11 | All | 50 | | ns | | | | | | | | | | | | | | STB to buffer full | tSBF| |9, 10, 11 | All | | 400 | ns | | | | | | | | | | | | | | STB width | tSS| |9, 10, 11 | All |200 | | ns | | | | | | | See fo