DLA SMD-5962-84100 REV F-2011 MICROCIRCUIT DIGITAL HIGH-SPEED CMOS DUAL 4-BIT BINARY COUNTER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED B Convert to military drawing format. Add case outline 2 (square chip carrier package) for vendor CAGE number 27014. Editorial changes throughout. 88-03-23 M. A. Frye C Changes to 1.3 and 1.4. Add vendor CAGE 18324 for device types 01CX, 01DX, and

2、012X. Device types 01CX and 012X inactive for new design; use M38510/66309BCX and M38510/66309B2X. Timing waveform: Correct clock A waveform. Editorial change in 6.4. Editorial changes throughout.89-01-11 M. A. Frye D Update boilerplate to MIL-PRF-38535 requirements. - CFS 02-01-22 Thomas M. Hess E

3、Made change to paragraph 3.5. Update boilerplate to MIL-PRF-38535 requirements. LTG 05-03-17 Thomas M. Hess F Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 11-06-22 David J. Corbett CURRENT CAGE CODE 67268 REV SHET REV SHET REV STATUS REV F F F F F F F F F F F F OF S

4、HEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Donald B. Osborne DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY D. A.

5、DiCenzo APPROVED BY N. A. Hauck MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, DUAL 4-BIT BINARY COUNTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 84-09-26 REVISION LEVEL F SIZE A CAGE CODE 14933 84100 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E391-11 Provided by IHSNot for ResaleNo reproduction or networki

6、ng permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84100 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcir

7、cuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 84100 01 C A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the cir

8、cuit function as follows: Device type Generic number Circuit function 01 54HC393 Dual 4-bit binary counter 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style B GDFP4-F14 14 Flat packC GDIP1-T14 or

9、 CDIP2-T14 14 Dual-in-line D GDFP1-F14 or CDFP2-F14 14 Flat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) . -0.5 V dc to +7.0 V dc DC input voltage ra

10、nge (VIN) . -0.5 V dc to VCC+ 0.5 V dc DC output voltage range (VOUT) -0.5 V dc to VCC+ 0.5 V dc Clamp diode current 20 mA DC output current (per pin) . 25 mA DC VCCor GND current (per pin) 50 mA Storage temperature range (TSTG) -65C to +150C Maximum power dissipation (PD) 500 mW 4/ Lead temperature

11、 (soldering, 10 seconds) . +260C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) . +175C _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliabil

12、ity. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ The limits for the parameters specified herein shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 4/ For TC= +100C to + 125C, derate linearly at 12 mW/C. Provided by IHSNot for Resale

13、No reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84100 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (VCC) . +2.0 V dc to +6.0 V

14、dc Input voltage range (VIN) . 0.0 V to VCCOutput voltage range (VOUT) 0.0 V to VCCCase operating temperature range (TC) -55C to +125C Input rise and fall time (tr, tf): VCC= 2.0 V dc 0 to 1000 ns VCC= 4.5 V dc 0 to 500 ns VCC= 6.0 V dc 0 to 400 ns Minimum width of clock, or reset pulse (tw): TC= +2

15、5C; CL= 50 pF: VCC= 2.0 V dc 80 ns VCC= 4.5 V dc 16 ns VCC= 6.0 V dc 14 ns TC= -55C, +125C; CL= 50 pF: VCC= 2.0 V dc 120 ns VCC= 4.5 V dc 24 ns VCC= 6.0 V dc 20 ns Maximum clock frequency (fMAX): TC= +25C; CL= 50 pF: VCC= 2.0 V dc 5 MHz VCC= 4.5 V dc 25 MHz VCC= 6.0 V dc 29 MHz TC= -55C, +125C; CL=

16、50 pF: VCC= 2.0 V dc 3.4 MHz VCC= 4.5 V dc 17 MHz VCC= 6.0 V dc 20 MHz Minimum recovery time, clear to clock (trec): TC= +25C; CL= 50 pF: VCC= 2.0 V dc 50 ns VCC= 4.5 V dc 10 ns VCC= 6.0 V dc 9 ns TC= -55C, +125C; CL= 50 pF: VCC= 2.0 V dc 75 ns VCC= 4.5 V dc 15 ns VCC= 6.0 V dc 13 ns Provided by IHS

17、Not for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84100 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks.

18、 The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manuf

19、acturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard

20、Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of

21、this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No. 7 - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX Advanced High-Speed CMOS D

22、evices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S Arlington, VA 22201). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited here

23、in, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A fo

24、r non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in

25、 accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function o

26、f the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimen

27、sions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on fi

28、gure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-

29、STANDARD MICROCIRCUIT DRAWING SIZE A 84100 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 5 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall ap

30、ply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, append

31、ix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38

32、535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed

33、 as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirement

34、s herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change

35、 that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option

36、of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84100 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics

37、. Test Symbol Test conditions -55C TC+125C unless otherwise specified 1/ Group A subgroups Limits Unit Min Max High level output voltage VOHVIN= VIHor VILIOH= -20 A VCC=2.0 V 1, 2, 3 1.9 V VCC=4.5 V 4.4 VCC=6.0 V 5.9 VIN= VIHor VILIOH= -4.0 mA VCC=4.5 V 3.7 VIN= VIHor VILIOH= -5.2 mA VCC=6.0 V 5.2 L

38、ow level output voltage VOLVIN= VIHor VILIOL= +20 A VCC=2.0 V 1, 2, 3 0.1 V VCC=4.5 V 0.1 VCC=6.0 V 0.1 VIN= VIHor VILIOL= +4.0 mA VCC=4.5 V 0.4 VIN= VIHor VILIOL= +5.2 mA VCC=6.0 V 0.4 High level input voltage VIH2/ VCC=2.0 V 1, 2, 3 1.5 V VCC=4.5 V 3.15 VCC=6.0 V 4.2 Low level input voltage VIL2/

39、CC=2.0 V 1, 2, 3 0.3 V VCC=4.5 V 0.9 VCC=6.0 V 1.2 Input capacitance CINVIN= 0.0 V, TC= +25C See 4.3.1c 4 10 pF Quiescent supply current ICCVCC= 6.0 V VIN= VCCor GND 1, 2, 3 160 A Input leakage current IINVCC= 6.0 V VIN= VCCor GND 1, 2, 3 1.0 A Functional tests See 4.3.1d 7 Propagation delay time, m

40、CLK input to mQAoutput, respectively tPHL1, tPLH13/ TC= +25C CL= 50 pF See figure 4 VCC=2.0 V 9 135 ns VCC=4.5 V 27 VCC=6.0 V 23 TC= -55C and +125C CL= 50 pF See figure 4 VCC=2.0 V 10, 11 205 VCC=4.5 V 41 VCC=6.0 V 35 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or net

41、working permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84100 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test conditions -55C TC+125C unless otherw

42、ise specified 1/ Group A subgroups Limits Unit Min Max Propagation delay time, mCLK input to mQDoutput, respectively tPHL2, tPLH23/ TC= +25C CL= 50 pF See figure 4 VCC=2.0 V 9 310 ns VCC=4.5 V 62 VCC=6.0 V 53 TC= -55C and +125C CL= 50 pF See figure 4 VCC=2.0 V 10, 11 465 VCC=4.5 V 93 VCC=6.0 V 79 Pr

43、opagation delay time, clear to any output (1CLR to 1Qn; 2CLR to 2Qn) tPHL33/ TC= +25C CL= 50 pF See figure 4 VCC=2.0 V 9 165 ns VCC=4.5 V 33 VCC=6.0 V 28 TC= -55C and +125C CL= 50 pF See figure 4 VCC=2.0 V 10, 11 250 VCC=4.5 V 56 VCC=6.0 V 43 Transition time high-to-low, low-to-high tTHL, tTLH4/ TC=

44、 +25C CL= 50 pF See figure 4 VCC=2.0 V 9 75 ns VCC=4.5 V 15 VCC=6.0 V 13 TC= -55C and +125C CL= 50 pF See figure 4 VCC=2.0 V 10, 11 110 VCC=4.5 V 22 VCC=6.0 V 19 1/ For a power supply of 5 V 10% the worst case output voltages (VOHand VOL) occur for HC at 4.5 V. Thus, the 4.5 V values should be used

45、when designing with this supply. Worst case VIHand VILoccur at VCC= 5.5 V and 4.5 V respectively. (The VIHvalue at 5.5 V is 3.85 V.) The worst case leakage current (IIN, and ICC) occur for CMOS at the higher voltage, and so the 6.0 V values should be used. 2/ VIHand VILtests are not required if appl

46、ied as a forcing function for VOHand VOL. 3/ AC testing at VCC= 2.0 V and VCC= 6.0 V shall be guaranteed, if not tested, to the limits specified in table I. 4/ Transition time (tTHL, tTLH), if not tested, shall be guaranteed to the specified parameters. Provided by IHSNot for ResaleNo reproduction o

47、r networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84100 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 8 DSCC FORM 2234 APR 97 Device type 01 Case outlines B, C, and D 2 Terminal number Terminal symbol 1 1CLK NC2 1CLR 1CLK 3 1QA1CLR4 1QB

48、1QA5 1QCNC6 1QD1QB7 GND NC8 2QD1QC9 2QC1QD10 2QBGND 11 2QANC 12 2CLR 2QD13 2CLK 2QC14 VCC2QB15 - NC 16 - 2QA17 - NC 18 - 2CLR 19 - 2CLK 20 - VCCNC = No internal connection Pin description Terminal symbol Description mCLK (m = 1 to 2) Clock inputs mCLR (m = 1 to 2) Clear inputs mQn (m = 1 to 2; n = A, B, C, or D) Data outputs FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCU