DLA DSCC-VID-V62 11613 REV B-2011 MICROCIRCUIT DIGITAL MIXED SIGNAL MICRCONTROLLER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO

2、 43218-3990 http:/www.dscc.dla.mil Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, MIXED SIGNAL MICRCONTROLLER, MONOLITHIC SILICON 11-10-27 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/11613 REV PAGE 1 OF 30 AMSC N/A 5962-V083-11 Provide

3、d by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11613 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance mixed signal microcontrol

4、ler microcircuit, with an operating temperature range of -40C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documen

5、tation: V62/11613 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 MSP430F2013 Mixed signal microcontroller 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter N

6、umber of pins JEDEC PUB 95 Package style X 15 JEDEC MO-220 Quad flatpack, No-leads 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold

7、 flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11613 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Voltage applied at VCCto VSS-0.3 V to +17 V Voltag

8、e apply to any pin -0.3 V to VCC+ 0.3 V 2/ Diode current at any device terminal . 2 mA Storage temperature 3/ Unprogrammed device -55C to 150C Programmed device -40C to 150C Thermal information 4/ Case outline letter X Units Junction to ambient thermal resistance(JA) 5/ 38.1 C/W Junction to case (to

9、p) thermal resistance (JCtop) 6/ 26 Juntion to board thermal resistance (JB) 7/ 7.5 Junction to top characterization parameter (JT) 8/ 0.3 Junction to board characterization parameter (JB) 9/ 5.7 Junction to case (bottom) thermal resistance (JCbot) 10/ 1.9 1.4 Recommended operating conditions. Suppl

10、y voltage (VCC) During program execution 1.8 V to 3.6 V During flash program/erase 2.2 V to 3.6 V Supply voltage (VSS) 0 V Operating free air temperature (TA) -40C to 125C Processor frequency (maximum MCLK frequency) 11/ 12/ VCC= 1.8 V, Duty cycle = 50% 10% 6 MHz VCC= 2.7 V, Duty cycle = 50% 10% 12

11、MHz VCC= 3.3 V, Duty cycle = 50% 10% 16 MHz 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended oper

12、ating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ All voltage referenced to VSS. The JTAG fuse blow voltage, VFBis allow to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the

13、 JTAG fuse. 3/ Higher temperature may be applied during board soldering according to the current JEDEC J-STD 020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. 4/ For more information about traditional and new thermal metric

14、s, see manufacturer data. 5/ The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC standard, high K board, as specified in JESD51-7, in an environment described in JESD51-2a. 6/ The junction to case (top) thermal resistance is obtained by simulati

15、ng a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 7/ The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperatur

16、e, as described in JESD51-8. 8/ The junction to top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (section 6 and 7). 9/ The junction to top character

17、ization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (section 6 and 7). 10/ The junction to case (bottom) thermal resistance is obtained by simulating a cold plate t

18、est on the exposed (power) pad. No specific JEDEC standard exists, but a close description can be found in the ANSI SEMI standard G30-88. 11/ This MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. 12/ Mod

19、ules might have a different maximum input clock specification of the respective module in manufacturer data sheet. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11613 REV

20、PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at h

21、ttp:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, C

22、AGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electri

23、cal performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3

24、.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Functional diagram. The functional diagram shall be as shown in figure 3. 3.5.4 Safe operating area. The safe operating area shall be as shown in figure 4. 3.5.5 Operating derate chart. The operating derate char

25、t shall be as shown in figure 5. 3.5.6 Active mode supply current (into Vcc). The active mode supply current (into VCC) shall be as shown in figure 6. 3.5.7 Typical characteristics - Output. The typical characteristics - Output shall be as shown in figure 7. 3.5.8 POR/Brownout Reset (BOR) vs Supply

26、voltage. The POR/Brownout Reset (BOR) vs Supply voltage shall be as shown in figure 8. 3.5.9 Typical characteristics POR/Brownout reset (BOR). The typical characteristics POR/Brownout reset (BOR) shall be as shown in figure 9. 3.5.10 Typical characteristics Calibrated 1 MHz DCO frequency. The typica

27、l characteristics Calibrated 1 MHz DCO frequency shall be as shown in figure 10. 3.5.11 Typical characteristics DCO clock wake up time from LPM3/4. The typical characteristics DCO clock wake up time from LPM3/4 shall be as shown in figure 11. Provided by IHSNot for ResaleNo reproduction or networkin

28、g permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11613 REV PAGE 5 3.5.12 Typical characteristics USI low level output voltage on SDA and SCL. The typical characteristics USI low level output voltage od SDA and SCL shall be as shown

29、 in figure 12. 3.5.13 Typical characteristics SD16 A SINAD performance over OSR. The typical characteristics SD16 A SINA performance over OSR shall be as shown in figure 13. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMB

30、US, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11613 REV PAGE 6 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ TAVCCLimits Unit Min Max Active Mode Supply Current into VCCExcluding External Current 3/ 4/ (See figure 5) Active mode (AM) Current (1 MHz) IAM, 1MHzfDCO=

31、fMCLK= fSMCLK= 1 MHz, fACLK= 32768 Hz, Program executes in flash, BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 2.2 V 280 A 3V 380 Active mode (AM) Current (1 MHz) IAM, 1MHzfDCO= fMCLK= fSMCLK= 1 MHz, fACLK= 32768 Hz, Program executes in RAM, BCSCTL1 = CALBC

32、1_1MHz, DCOCTL = CALDCO_1MHz, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 2.2 V 190 TYP A 3 V 265 TYP Active mode (AM) Current (4 kHz) IAM, 4kHzfMCLK= fSMCLK= fACLK= 32768 Hz/8 = 4096 Hz, fDCO= 0 Hz, Program executes in flash, SELMx = 11, SELS = 1, DIVMx = DIVSx = DIVAx = 11, CPUOFF = 0, SCG0 = 1, SC

33、G1 = 0, OSCOFF = 0 -40C to 85C 2.2 V 3 A 125C 2.2 V 6 -40C to 85C 3V 4 125C 3 V 7 Active mode (AM) Current (100 kHz) IAM, 100kHzfMCLK= fSMCLK= fDCO(0, 0) = 100 kHz, fACLK= 0 Hz, Program executes in flash, RSELx = 0, DCOx = 0, CPUOFF = 0, SCG0 = 1, SCG1 = 0, OSCOFF = 1 -40C to 85C 2.2 V 50 A 125C 2.2

34、 V 65 -40C to 85C 3V 55 125C 3 V 70 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11613 REV PAGE 7 TABLE I. Electrical performance character

35、istics - Continued. 1/ Test Symbol Conditions 2/ TAVCCLimits Unit Min Max Low Power mode supply Currents (Into VCC) Excluding External Current 3/ 4/ ( See figure 6 and 7) Low power mode 0 (LPM0) current 5/ ILPM0, 1MHzfMCLK= 0 MHz, fSMCLK= fDCO= 1 MHz fACLK= 32768 Hz, BCSCTL1 = CALBC1_1MHz, DCOCTL =

36、CALDCO_1MHz, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 2.2 V 86 A 3 V 108 Low power mode 0 (LPM0) current 5/ ILPM0, 100kHzfMCLK= 0 MHz, fSMCLK= fDCO(0, 0) 100 kHz fACLK= 0 Hz, RSELx = 0, DCOx = 0, CPUOFF = 1, SCG0 = 1, SCG1 = 0, OSCOFF = 1 2.2 V 52 A 3 V 56 Low power mode 2 (LPM2) current 6/ ILPM2f

37、MCLK= fSMCLK= 0 MHz, fDCO= 1 MHz fACLK= 32768 Hz, BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 -40C to 85C 2.2 V 29 A 125C 34 -40C to 85C 3 V 32 125C 37 Low power mode 3 (LPM3) current 5/ ILPM3,LFXT1fDCO = fMCLK = fSMCLK = 0 MHz fACLK= 32768 Hz, CPUOFF = 1,

38、 SCG0 = 1, SCG1 = 1, OSCOFF = 0 -40C 2.2 V 1.2 A 25C 1 85C 2.3 125C 6.5 -40C 3 V 1.2 25C 1.2 85C 28 125C 7.6 Low power mode 3 (LPM3) current 6/ ILPM3,VLOfDCO = fMCLK = fSMCLK = 0 MHz fACLKfrom internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 -40C 2.2 V 0.7 A 25C 0.7 85C 1.6 1

39、25C 5.5 -40C 3 V 0.9 25C 0.9 85C 1.8 125C 6.5 Low power mode 3 (LPM4) current 7/ ILPM3,VLOfDCO = fMCLK = fSMCLK = 0 MHz fACLK= 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 -40C 2.2 V/3 V 0.5 A 25C 0.5 85C 1.5 125C 4.4 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or

40、 networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11613 REV PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ VCCLimits Unit Min Max Schmitt Trigger Inputs (Ports P1 and P2) P

41、ositive going input threshold voltage VIT+0.45 VCC0.75 VCCV 2.2 V 1.00 1.65 3 V 1.35 2.25 Negative going input threshold voltage VIT+0.25 VCC0.55 VCCV 2.2 V 0.55 1.20 3 V 0.75 1.65 Input voltage hysteresis (VIT+ - VIT-)Vhys2.2 V 0.2 1.0 V 3 V 0.3 1.0 Pullup/Pulldown resistor RPullFor pullup: VIN= VS

42、S, For pulldown: VIN= VCC20 50 k Input capacitance CIVIN= VSSor VCC5 TYP pF Inputs (Ports P1 and P2) External interrupt timing t(int)Port P1, P2: P1.x to P2.x, External trigger pulse width to set interrupt flag 8/ 2.2 V/3 V 25 ns Leakage current (Ports P1 and P2) High impedance leakage current Ilkg(

43、Px.y)9/ 10/ 2.2 V/3 V 50 nA Outputs (Ports P1 and P2) See figure 6 and 7 High level output voltage VOHI(OHmax) = -1.5 mA 11/ 2.2 V VCC 0.25 VCCV I(OHmax) = -6 mA 12/ 2.2 V VCC 0.6 VCCI(OHmax) = -1.5 mA 11/ 3 V VCC 0.25 VCCI(OHmax) = -6 mA 12/ 3 V VCC 0.6 VCCLow level output voltage VOLI(OLmax) = 1.5

44、 mA 11/ 2.2 V VSSVSS+ 0.25 V I(OLmax) = 6 mA 12/ 2.2 V VSSVSS+ 0.6 I(Olmax) = 1.5 mA 11/ 3 V VSSVSS+ 0.25 I(Olmax) = 6 mA 12/ 3 V VSSVSS+ 0.6 Output frequency (Ports P1 and P2) Port output frequency (with load) fPx.yP1.4/SMCLK, CL= 20 pF, RL= 1 k 13/ 14/ 2.2 V 10 MHz 3 V 12 Clock output frequency fP

45、ortCLKP2.0/ACLK, P1.4/SMCLK, CL= 20 pF 14/ 2.2 V 12 MHz 3 V 16 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11613 REV PAGE 9 TABLE I. Elect

46、rical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ VCCLimits Unit Min Max POR/Brownout Reset (BOR) 15/ See figure 8 VCC(start)dVCC/dt 3 V/s 0.7 x V(B_IT-)TYP V See figure 8 to 10 V(B_IT-)dVCC/dt 3 V/s 1.71 V See figure 8 Vhys(B_IT-)dVCC/dt 3 V/s 70 210 mV See figure 8 td(BOR

47、)s Pulse length needed at RST/NMI pin to accepted reset internally 16/ s DCO frequency Supply voltage VCCRSELx 90 TYP dB SD16GAINx = 32, Common mode input signal: VID= 16 mV, fIN= 50 Hz, 100 Hz 75 TYP DC power supply rejection DC PSR SD16GAINx = 1, VIN= 500 mV, VCC= 2.5 V to 3.6 29/ 2.5 V to 3.6 V 0.35 TYP %/V AC power supply rejection ratio AC PSRR SD16GAINx = 1, VCC= 3 V 10 mV, fIN= 50 Hz 3 V 80 TYP dB See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE