DLA DSCC-VID-V62 11611 REV A-2011 MICROCIRCUIT DIGITAL-LINEAR 12-BIT ANALOG TO DIGITAL CONVERTER MONOLITHIC SILICON.pdf

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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECK

2、ED BY RAJESH PITHADIA TITLE MICROCIRCUIT, DIGITAL-LINEAR, 12-BIT ANALOG TO DIGITAL CONVERTER, MONOLITHIC SILICON 11-07-26 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/11611 REV PAGE 1 OF 14 AMSC N/A 5962-V056-11 Provided by IHSNot for ResaleNo reproduction or networking per

3、mitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11611 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 12 bit analog to digital converter microcircuit, with an operating temperature r

4、ange of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/11611 - 01 X E Drawing Device type Ca

5、se outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 AD7476-EP 12 bit analog to digital converter 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X

6、6 MO-178-AB Plastic small outline surface mount 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IH

7、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11611 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage (VDD) to ground (GND) -0.3 V to +7 V Analog input voltage to GND -0.3 V to

8、 VDD+ 0.3 V Digital input voltage to GND . -0.3 V to 7 V Digital output voltage to GND . -0.3 V to VDD+ 0.3 V Input current to any pin except supplies . 10 m A 2/ Junction temperature range (TJ) 150C Storage temperature range (TSTG) -65C to +150C Lead temperature, soldering reflow (10 seconds to 30

9、seconds) . 235C Lead (Pb) free temperature, soldering reflow . 255C Electrostatic discharge (ESD) 3.5 kV Thermal resistance, junction to ambient (JC) 92C/W Thermal resistance, junction to ambient (JA) 230C/W 1.4 Recommended operating conditions. 3/ 4/ Supply voltage (VDD) range . +2.35 V to +5.25 V

10、Operating free-air temperature range (TA) . -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “rec

11、ommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Transient currents of up to 100 mA do not cause silicon controlled rectifier (SCR) latch up. 3/ Use of this product beyond the manufacturers design rule

12、s or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 4/ All ratings and specifications, please refer to the relevant EP datasheet. Provided by IHSNot for ResaleNo reproduction or netwo

13、rking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11611 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the JEDEC Office,

14、 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 ide

15、ntifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristic

16、s are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The

17、 terminal connections shall be as shown in figure 2. 3.5.3 Load circuit for digital output timing specifications. The load circuit for digital output timing specifications shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,

18、-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11611 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max Dynamic performance section. fIN= 100 kHz sine wave Signal to (noise + distortion

19、) SINAD +25C 01 70 dB -55C to +125C 69 Signal to noise ratio SNR -55C to +125C 01 70 dB Total harmonic distortion THD -55C to +125C 01 -78 typical dB Peak harmonic or spurious noise SFDR -55C to +125C 01 -80 typical dB Intermodulation distortion, second order terms IMD fa = 103.5 kHz, fb = 113.5 kHz

20、 -55C to +125C 01 -78 typical dB Intermodulation distortion, third order terms IMD fa = 103.5 kHz, fb = 113.5 kHz -55C to +125C 01 -78 typical dB Aperture delay -55C to +125C 01 10 typical ns Aperture jitter -55C to +125C 01 30 typical ps Full power bandwidth FPBW At 3 dB -55C to +125C 01 6.5 typica

21、l MHz DC accuracy section. VDD= 2.35 V to 3.6 V 3/ Resolution -55C to +125C 01 12 Bits Integral nonlinearity INL +25C 01 0.6 typical LSB -55C to +125C 1.5 Differential nonlinearity DNL Guaranteed in missed codes to +25C 01 0.75 typical LSB 12 bits -55C to +125C -0.9 +1.5 Offset error OE -55C to +125

22、C 01 2 LSB Gain error GE -55C to +125C 01 2 LSB Analog input section. Input voltage ranges VIN-55C to +125C 01 0 to VDDV DC leakage current -55C to +125C 01 1 A Input capacitance CIN-55C to +125C 01 30 typical pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networki

23、ng permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11611 REV PAGE 6 TABLE I. Electrical performance characteristics - continued. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max Logic input section. Input h

24、igh voltage VINH-55C to +125C 01 2.4 V VDD= 2.35 V 1.8 Input low voltage VINLVDD= 3 V -55C to +125C 01 0.4 V VDD= 5 V 0.8 Input current, SCLK pin IINTypically 10 nA, VIN= 0 V or VDD-55C to +125C 01 1 A Input current, CS pin IIN-55C to +125C 01 1 typical A Input capacitance CIN4/ -55C to +125C 01 10

25、pF Logic output section. Output high voltage VOHISOURCE= 200 A, VDD= 2.35 V to 5.25 V -55C to +125C 01 VDD 0.2 V Output low voltage VOLISINK= 200 A -55C to +125C 01 0.4 V Floating state leakage current -55C to +125C 01 10 A Floating state output capacitance 4/ -55C to +125C 01 10 pF Output coding St

26、raight (natural) binary -55C to +125C 01 Conversion rate section. Conversion time 16 SCLK -55C to +125C 01 1.33 s Track and hold acquisition time Full scale step input -55C to +125C 01 500 ns Sine wave input 100 kHz 400 Throughput rate -55C to +125C 01 600 kSPS See footnotes at end of table. Provide

27、d by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11611 REV PAGE 7 TABLE I. Electrical performance characteristics - continued. 1/ Test Symbol Conditions 2/Temperature, TADevice type

28、 Limits Unit Min Max Power requirements section. Supply voltage VDD-55C to +125C 01 2.35 5.25 V Supply current, normal mode (static) IDDDigital I/Ps = 0 V or VDD, VDD= 4.75 V to 5.25 V, SCLK on or off -55C to +125C 01 2 typical mA Digital I/Ps = 0 V or VDD, VDD= 2.35 V to 3.6 V, SCLK on or off 1 typ

29、ical Supply current, normal mode (operational) IDDDigital I/Ps = 0 V or VDD, VDD= 4.75 V to 5.25 V, fSAMPLE= fSAMPLEmax 5/ -55C to +125C 01 3 mA Digital I/Ps = 0 V or VDD, VDD= 2.35 V to 3.6 V, fSAMPLE= fSAMPLEmax 5/ 1.4 Full power down mode FPDM SCLK off -55C to +125C 01 1 A SCLK on 80 Power dissip

30、ation, normal mode (operational) PDVDD= 5 V, fSAMPLE= fSAMPLEmax 5/ -55C to +125C 01 15 mW VDD= 3 V, fSAMPLE= fSAMPLEmax 5/ 4.2 Power dissipation, full power down PDVDD= 5 V, SCLK off -55C to +125C 01 5 W VDD= 3 V, SCLK off 3 See footnotes at end of table. Provided by IHSNot for ResaleNo reproductio

31、n or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11611 REV PAGE 8 TABLE I. Electrical performance characteristics - continued. 1/ Test Symbol Conditions 6/ 7/Temperature, TADevice type Limits Unit Min Max Timing speci

32、fications section. Serial clock 8/ frequency fSCLKAt 3 V -55C to +125C 01 10 kHz At 5 V 10 At 3 V 12 MHz At 5 V 12 Conversion time tCONVERTAt 3 V -55C to +125C 01 16 x tSCLKAt 5 V 16 x tSCLKMinimum quite time required between bus relinquish and start of next conversion tQUIETAt 3 V -55C to +125C 01

33、50 ns At 5 V 50 Minimum CS pulse width t1At 3 V -55C to +125C 01 10 ns At 5 V 10 CS to SCLK setup time t2At 3 V -55C to +125C 01 10 ns At 5 V 10 Delay from CS 9/ until SDATA three state disabled t3At 3 V -55C to +125C 01 20 ns At 5 V 20 Data access time 9/ after SCLK falling edge, A version t4At 3 V

34、 -55C to +125C 01 40 ns At 5 V 20 Data access time 9/ after SCLK falling edge, B version t4At 3 V -55C to +125C 01 70 ns At 5 V 20 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZ

35、E A CODE IDENT NO. 16236 DWG NO. V62/11611 REV PAGE 9 TABLE I. Electrical performance characteristics - continued. 1/ Test Symbol Conditions 6/ 7/Temperature, TADevice type Limits Unit Min Max Timing specifications section - continued. SCLK low pulse width t5At 3 V -55C to +125C 01 0.4 x tSCLKns At

36、5 V 0.4 x tSCLKSCLK high pulse width t6At 3 V -55C to +125C 01 0.4 x tSCLKns At 5 V 0.4 x tSCLKSCLK to data valid hold time t7At 3 V -55C to +125C 01 10 ns At 5 V 10 SCLK falling edge 10/ to SDATA high impedance t8At 3 V -55C to +125C 01 10 25 ns At 5 V 10 25 Power up time from full power down tPOWE

37、R-UPAt 3 V -55C to +125C 01 1 typical s At 5 V 1 typical 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all paramet

38、ers may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Unless otherwise specified, VDD= 2.35 V to 5.25 V, fSCLK= 12 MHz, and fSAMPLE= 600 kSPS 3/ Specifications apply as typical figures when VDD= 5.25 V.

39、4/ Guaranteed by characterization. 5/ fSAMPLEmax = 600 kSPS. 6/ 3 V specifications apply from VDD= 2.35 V to 3.6 V and 5 V specifications apply from VDD= 4.75 V to 5.25 V. 7/ Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns ( 10% to 90% of VDD) and timed from a vol

40、tage level of 1.6 V. 8/ Mark/space ratio for the SCLK input is 40/60 to 60/40. 9/ Measured with the load circuit of figure 3 and defined as the time required for the output to cross 0.8 V to 2.0 V. 10/ t8 is derived from the measured time taken by the data output to change 0.5 V when loaded with the

41、 circuit in figure 3. The measured number is then extrapolated to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, is the true bus relinquish time of the part and is independent of the bus loading. Provided by IHSNot for ResaleNo reproduction or networ

42、king permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11611 REV PAGE 10 Case X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS,

43、OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11611 REV PAGE 11 Case X continued. Symbol Dimensions Inches Millimeters Min Max Min Max A 0.035 0.051 0.90 1.30 A1 0.001 0.005 0.05 0.15 A2 0.037 0.057 0.95 1.45 b 0.011 0.019 0.30 0.50 c 0.003 0.007 0.08 0.20 D 0.110 0.118 2.80 3.00 E 0.059 0.069 1.50 1

44、.70 E1 0.102 0.118 2.60 3.00 e 0.037 BSC 0.95 BSC L 0.013 0.021 0.35 0.55 L1 0.023 BSC 0.60 BSC NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2. Falls within reference to JEDEC MO-178-AB. FIGURE 1. Case outline - Continued. Provided by IHSNot for Resa

45、leNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11611 REV PAGE 12 Device type 01 Case outline X Terminal number Terminal symbol Description 1 VDDPower supply input. The VDDrange for the device is from

46、 2.35 V to 5.25 V. 2 GND Analog ground. Ground reference point for all circuitry on the part. All analog input signals should be referred to this GND voltage. 3 VINAnalog input. Single ended analog input channel. The input range is 0 V to VDD. 4 SCLK Serial clock. Logic input. SCLK provides the seri

47、al clock for accessing data from the part. This clock input is also used as the clock source for the device conversion process. 5 SDATA Data out. Logic output. The conversion result is provided on this output as serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the device consists of four leading zeros followed by the 12 bits of conversion data; this is provided MSB first. 6 CS Chip select. Acti