DLA DSCC-VID-V62 11610-2011 MICROCIRCUIT LINEAR CMOS OPERATIONAL AMPLIFIER MONOLITHIC SILICON.pdf
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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY RAJ
2、ESH PITHDIA TITLE MICROCIRCUIT, LINEAR, CMOS, OPERATIONAL AMPLIFIER, MONOLITHIC SILICON 11-09-20 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/11610 REV PAGE 1 OF 11 AMSC N/A 5962-V074-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr
3、om IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11610 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance CMOS operational amplifier microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor
4、 Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/11610 - 01 X E Drawing Device type Case outline Lead finish number (Se
5、e 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 OPA365-EP CMOS 50 MHz gain bandwidth operational amplifier 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 5 MO-178-AA Plastic
6、 small outline surface mount 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo r
7、eproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11610 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage (VS) 5.5 V Signal input terminals, voltage . (-V) 0.5 V to (+V) + 0.5 V 2/ Signal input termi
8、nals, current 10 mA 2/ Output short circuit duration . Continuous 3/ 4/ Power dissipation (PD) . 56.25 mW Junction temperature range (TJ) +150C Storage temperature range (TSTG) -65C to +150C Electrostatic discharge (ESD) rating: Human body model (HBM) . 4000 V Charged device model (CDM) 1000 V Machi
9、ne model (MM) . 200 V Thermal resistance, junction to case (JC) . 69.4C/W Thermal resistance, junction to ambient (JA) 200C/W typical 1.4 Recommended operating conditions. 5/ Supply voltage range (VS) 2.2 V to 5.5 V Operating free-air temperature range (TA) . -55C to +125C 1/ Stresses beyond those l
10、isted under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated co
11、nditions for extended periods may affect device reliability. 2/ Input terminals are diode clamped to the power supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should be current limited to 10 mA or less. 3/ Short circuit to ground, one amplifier per package. 4/ Cont
12、inuous output current greater than 20 mA for extended periods may affect product reliability. 5/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyo
13、nd the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11610 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconducto
14、r Devices (Applications for copies should be addressed to the JEDEC Office, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 he
15、rein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and
16、 recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outli
17、ne shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V
18、62/11610 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max Offset voltage Input offset voltage VOS+25C 01 200 V -55C to +125C 450 Input offset voltage drift dVOS/ dT -55C to +125C 01 3 typical V / C Input offset vol
19、tage versus power supply PSRR VS= +2.2 V to +5.5 V -55C to +125C 01 100 V/V Input bias current Input bias current IB+25C 01 10 pA -55C 0.5 typical +125C 60 typical Input offset current IOS+25C 01 10 pA Noise Input voltage noise enf = 0.1 Hz to 10 Hz +25C 01 5 typical VPPInput voltage noise density e
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