DLA DSCC-VID-V62 10603 REV A-2009 MICROCIRCUIT DIGITAL CMOS 3 0 V TO 5 5 V 12 BIT 200 KSPS 4- 8 CHANNEL LOW POWER SERIAL ANALOG TO DIGITAL CONVERTER WITH AUTOPOWER DOWN MONOLITHIC .pdf

《DLA DSCC-VID-V62 10603 REV A-2009 MICROCIRCUIT DIGITAL CMOS 3 0 V TO 5 5 V 12 BIT 200 KSPS 4- 8 CHANNEL LOW POWER SERIAL ANALOG TO DIGITAL CONVERTER WITH AUTOPOWER DOWN MONOLITHIC .pdf》由会员分享，可在线阅读，更多相关《DLA DSCC-VID-V62 10603 REV A-2009 MICROCIRCUIT DIGITAL CMOS 3 0 V TO 5 5 V 12 BIT 200 KSPS 4- 8 CHANNEL LOW POWER SERIAL ANALOG TO DIGITAL CONVERTER WITH AUTOPOWER DOWN MONOLITHIC .pdf（12页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY MM D

2、D CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, CMOS, 3.0 V TO 5.5 V, 12 BIT, 200 KSPS, 4-/8 CHANNEL, LOW POWER SERIAL ANALOG TO DIGITAL CONVERTER WITH AUTOPOWER DOWN, MONOLITHIC SILICON 09-11-09 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/10603 REV PAGE 1 OF 12 AMSC

3、N/A 5962-V011-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10603 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high per

4、formance 3.0 V to 5.5 V, 12 bit, 200 KSPS, 4-/8 channel, low power serial analog to digital converter with auto power down microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. T

5、he vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/10603 - 01 X A Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TLV2

6、548-EP 3.0 V to 5.5 V, 12 bit, 200 KSPS, 4-/8 channel, low power serial analog to digital converter with auto power down 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 JEDEC MO-153 Plastic Small outline 1.2.3 Lead finis

7、hes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted witho

8、ut license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10603 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (GND to VCC) . -0.3 V to 6.5 V Analog input voltage range, . -0.3 V to VCC+ 0.3 V Reference input voltage . VCC+ 0.3 V

9、 Digital input voltage range -0.3 V to VCC+ 0.3 V Operating virtual junction temperature range, TJ-55C to 150C Operating free air temperature range, TA. -55C to 125C Storage temperature range (TSTG) . -65C to 150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds . 260C Dissipation rating

10、s: Package TA 25C Power rating Derating factor Above TA= 25C 2/ TA= 125C power rating Case outline X 977 mW 7.8 mW/C 195 mW 1.4 Recommended operating conditions. 3/ Parameter Symbol Min Max Unit Supply voltage VCC3.0 5.5 V Analog input voltage 4/ 0 VCCV High level control input voltage VIH2.1 V Low

11、level control input voltage VIL0.6 V Delay time, delay from falling edge to FS rising edge (See figure 4) td(CSL-FSH)0.5 SCLKs Delay time, delay from 16thSCLK falling edge to rising edge (FS = 1), or 17thrising edge (FS is active) (See figure 4 and 7) td(SCLK-CSH)0.5 SCLKs Setup time, FS rising edge

12、 before SCLK falling edge (See figure 4) tsu(FSH-SCLKL)20 ns Hold time, FS hold high after SCLK falling edge (See figure 4) th(FSH-SCLKL)30 ns Pulse width, high time (See figure 4 and 7) twH(CS) 100 ns Pulse width, FS high time (See figure 4) twH(FS)0.75 SCLKs SCLK cycle time (See figure 4 and 7) VC

13、C= 3.0 V to 3.6 V tc(SCLK)67 10000 ns VCC= 4.5 V to 5.5 V 50 10000 ns 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicat

14、ed under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ This is the inverse of the traditional junction to ambient thermal resistance (RJA). Thermal resistance is not production tested and the va

15、lue given are for informational purposes only. 3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 4/ When binary output for

16、mat is used, analog input voltages greater than that applied to REFP convert as all ones (111111111111), while input voltages less than that applied to REFM convert as all zeros (000000000000). The device is functional with reference down to 1 V. (VREFP VREFM 1); however, the electrical specificatio

17、ns are no longer applicable. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10603 REV PAGE 4 1.4 Recommended operating conditions - Continued. 3/ Parameter Symbol

18、 Min Max Unit Pulse width, SCLK low time (See figure 4 and 7) VCC= 4.5 V twL(SCLK)22 ns VCC= 3.0 V 27 Pulse width, SCLK high time (See figure 4 and 7) VCC= 4.5 V twH(SCLK)22 VCC= 3.0 V 27 Setup time, SDI valid before failing edge of SCLK (FS is active) or the rising edge of SCLK (FS = 1) (See figure

19、 7) tsu(DI-SCLK)25 Hold time, SDI hold valid after failing edge of SCLK (FS is active) or the rising edge of SCLK (FS = 1) (See figure 7) th(DI-SCLK)5 Delay time, delay from falling edge to SDO valid (See figure 4 and 7) td(CSL-DOV)25 Delay time, delay from FS falling edge to SDO valid (See figure 4

20、) td(FSL-DOV)25 Delay time, delay from SCLK falling edge (FS is active) or SCLK rising edge (FS = 1) to SDO valid (See figure 4 and 7) For a date code later than xxx, see the data code from manufacturer data. VCC= 5.5 V SDO = 0 pF td(SCLK-DOV)0.5 SCLK + 5 TYP SDO = 60 pF 0.5 SCLK + 24 VCC= 3.0 V SDO

21、 = 0 pF 0.5 SCLK + 12 TYP SDO = 60 pF 0.5 SCLK + 33 Delay time, delay from 17thSCLK rising edge (FS is active), or the 16thfalling edge (FS = 1) to EOC falling edge (See figure 4 and 7) td(SCLK-EOCL)45 TYP Delay time, delay from 16thSCLK falling edge to falling edge (FS = 1), or from the 17thrising

22、edge SCLK to rising edge. (See figure 4, 5, 6, and 7) td(SCLK-INTL)Min t(conv)Delay time, delay from falling edge or FS rising edge to rising edge (See figure 4, 5, 6, and 7) td(CLK-INTH)or td(FSH-INTH)50 Delay time, delay from rising edge to falling edge (See figure 5 and 6) td(CSH-CSTARTL)100 Dela

23、y time, delay from rising edge to EOC falling edge (See figure 5 and 6) td(CSTARTH-EOCL)50 ns Pulse width, low time (See figure 5 and 6) twL(CSTART) Min t(sample) s Delay time, delay from rising edge to falling edge (See figure 6) td(CSTARTH-CSTARTL)Min t(conv)s Delay time, delay from rising edge to

24、 falling edge (See figure 6 and 7) td(CSTARTH-INTL)Max t(conv)TYP s Operation free air temperature TA-55 125 C Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/1060

25、3 REV PAGE 5 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marki

26、ng. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers pa

27、rt number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construc

28、tion, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Functional block diagram. The functional block diagram shall be

29、 as shown in figure 3. 3.5.4 Timing waveforms. The timing waveforms shall be as shown in figure 4 - 7. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10603 REV PA

30、GE 6 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ Limits Unit Min Max High level output voltage VOHVCC= 5.5 V, IOH= -0.2 mA at 30 pF load 2.4 V VCC= 3.0 V, IOH= -20 A at 30 pF load VCC 0.2 Low level output voltage VOLVCC= 5.5 V, IOL= 0.8 mA at 30 pF load 0.4 VCC= 3.0

31、 V, IOL= 20 A at 30 pF load 0.1 Off state output current (high-impedance state) IOZVO= VCC= VCC2.5 A VO= 0 = VCC-2.5 High level input current IIHVI= VCC2.5 Low level input current IILVI= 0 V 2.5 Operating supply current, normal short sampling ICCat 0 V, Ext ref VCC= 4.5 V to 5.5 V 2 mA VCC= 3.0 V to

32、 3.3 V 1 at 0 V, Int ref VCC= 4.5 V to 5.5 V 2.4 VCC= 3.0 V to 3.3 V 1.7 Operating supply current, extended sampling at 0 V, Ext ref VCC= 4.5 V to 5.5 V 1.1 TYP VCC= 3.0 V to 3.3 V 1 TYP at 0 V, Int ref VCC= 4.5 V to 5.5 V 2.1 TYP VCC= 3.0 V to 3.3 V 1.6 TYP Power down supply current for all digital

33、 input, 0 VI 0.3 V or VI VCC 0.3 V, SCLK = 0 ICC(PD)VCC= 4.5 V to 5.5 V, Ext clock 1 TYP A VCC= 3.0 V to 3.3 V, Ext clock 1 TYP Auto power down current for all digital input, 0 VI 0.3 V or VI VCC 0.3 V, SCLK = 0 ICC(AUTOPWDN)VCC= 4.5 V to 5.5 V, Ext clock, Ext ref 1.0 TYP 3/ VCC= 3.0 V to 3.3 V, Ext

34、 clock, Ext ref 1.0 TYP 4/ Selected channel leakage current Selected channel at VCC2.5 Selected channel at 0 V 2.5 Maximum static analog reference current into REFP (use external reference) VREFP = VCC= 5.5 V, VREFM = GND 1 TYP Input capacitance CiAnalog inputs 50 pF Control inputs 25 Input MUX ON r

35、esistance ZiVCC= 4.5 V 500 VCC= 2.7 V 600 AC specifications Signal to noise ratio + distortion SINAD fI = 12 kHz at 200 KSPS 65 dB Total harmonic distortion THD fI = 12 kHz at 200 KSPS TA= -55C -73 All other temperature -75 Effective number of bits ENOB fI = 12 kHz at 200 KSPS 11.6 TYP Bits Spurious

36、 free dynamic range SFDR fI = 12 kHz at 200 KSPS -75 dB Analog input Full power bandwidth, -3 dB 1 TYP MHz Full power bandwidth, -1 dB 500 TYP kHz See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, C

37、OLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10603 REV PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ Limits Unit Min Max Reference specifications 5/ (0.1 F and 10 F between REFP and REFM pins) Positive reference input voltage REFP

38、VCC= 3.0 V to 3.3 V 2 VCCV Negative reference input voltage REFM VCC= 3.0 V to 3.3 V 0 2 Reference input impedance VCC= 5.5 V = 1, SCLK = 0, (off) 100 M = 0, SCLK = 20 MHz, (on) 20 k VCC= 3 V = 1, SCLK = 0, (off) 100 M = 0, SCLK = 15 MHz, (on) 20 k Reference input voltage difference REFP - REFM VCC=

39、 3.0 V to 5.5 V 2 VCCV Internal reference voltage REFP - REFM VCC= 5.5 V VREF SELECT = 4 V 3.85 4.15 V VCC= 5.5 V VREF SELECT = 2 V 1.925 2.075 VCC= 3.0 V VREF SELECT = 2 V 1.925 2.075 Internal reference start up time VCC= 5.5 V, 3 V with 10 F compensation cap 20 TYP ms Internal reference temperatur

40、e coefficient 40 5/ PPM/ C Operating characteristics Integral linearity error (INL) 6/ EL 1.2 LSB Differential linearity error (DNL) ED 7/ 1.2 Offset error 8/ EO 7/ TA= 25C and 125C -4 6 TA= -55C -4 6.2 Full scale error 8/ EFS 7/ TA= 25C and 125C -4 6 TA= -55C -4 7.6 Self test output code 9/ SDI = B

41、000h 800 h (2048D) SDI = C000h 000h (0D) SDI = D000h FFFh (4095D) Conversion time Internal OSC t(conv)4.65 s External SCLK (14 x DIV) / fSCLKSampling time t(sample)With a maximum of 1 kW input source impedance 600 ns 1/ Testing and other quality control techniques are used to the extent deemed neces

42、sary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or

43、design. 2/ Over operating free air temperature range, VCC= VREFP= 3 V to 5.5 V, VREFM= 0 V, SCLK frequency = 20 MHz at 5 V, 15 MHz at 3 V (unless otherwise noted). All typical values are at VCC= 5 V, TA= 25C 3/ 1.2 mA if internal reference is used, 165 A if internal clock is used. 4/ 0.8 mA if inter

44、nal reference is used, 116 A if internal clock is used. 5/ Specified by design. 6/ Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics. 7/ Analog input voltages greater than that applied to REFP convert as all ones (111111111111), while input vo

45、ltages less than that applied to REFM convert as all zeros (000000000000). 8/ Zero error is the difference between 000000000000 and the converted output for zero input voltage: full scale error is the difference between 111111111111 and the converted output for full scale input voltage. 9/ Both the

46、input data and the output codes are expressed in positive logic. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10603 REV PAGE 8 Case X Dimensions Symbol Millimet

47、ers Symbol Millimeters Min Max Min Max A 1.20 E 4.30 4.50 A1 0.05 0.15 E1 6.20 6.60 b 0.19 0.30 e 0.65 BSC c 0.15 NOM L 0.50 0.75 D 6.40 6.60 NOTES: 1. All linear dimensions are in millimeters 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protru

48、sion not to exceed 0.15. 4. Falls within JEDEC MO-153. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10603 REV PAGE 9 Case outlines X Terminal number Terminal symbol Terminal number Terminal symbol 1 SDO 11 A5 2 SDI 12 A6 3 SCLK