DLA DSCC-VID-V62 09626 REV A-2010 MICROCIRCUIT DIGITAL-LINEAR 16 CHANNEL 24 BIT ANALOG TO DIGITAL CONVERTER MONOLITHIC SILICON.pdf
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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Add device type 02 and case outline Y. - ro 10-01-07 C. SAFFLE Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV A A A A A PAGE 18 19 20 21 22 REV STATUS OF PAGES REV A A A A A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13
2、14 15 16 17 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, DIGITAL-LINEAR, 16 CHANNEL, 24 BIT ANALOG TO DIGITAL CONVERTER, MONOLITHIC SILICON 09-05-12 APPROVED BY JOSEPH D. RO
3、DENBECK SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09626 REV A PAGE 1 OF 22 AMSC N/A 5962-V021-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09626 REV A PAGE 2
4、1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 16 channel, 24 bit analog to digital converter (ADC) microcircuit, with an operating temperature range of -55C to +125C for device type 01 and -40C to +105C for device type 02. 1.2 Vendor Item Drawing Administr
5、ative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/09626 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (S
6、ee 1.2.3) 1.2.1 Device type(s). Device type Generic Temperature range Circuit function 01 ADS1258M-EP -55C to +125C 16 channel, 24 bit analog to digital converter 02 ADS1258IP-EP -40C to +105C 16 channel, 24 bit analog to digital converter 1.2.2 Case outline(s). The case outline(s) are as specified
7、herein. Outline letter Number of pins JEDEC PUB 95 Package style X 48 See figure 1 Plastic square leadless chip carrier with thermal pad Y 48 MS-026 Plastic quad flat pack with thermal pad 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device
8、manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236
9、DWG NO. V62/09626 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Positive analog power supply (AVDD) to negative analog power supply (AVSS) . -0.3 V to 5.5 V AVSSto digital ground (DGND) -2.8 V to 0.3 V Digital power supply (DVDD) to DGND . -0.3 V to 5.5 V Input current, momentary . 100 mA Input curr
10、ent, continuous 10 mA Analog input voltage . AVSS 0.3 V to AVDD+ 0.3 V Digital input voltage to DGND -0.3 V to DVDD+ 0.3 V Maximum junction temperature (TJ) . +150C Storage temperature range -60C to +150C Thermal resistance, junction to case (JC) . 20C/W Thermal resistance, junction to ambient (JA)
11、: High K 33C/W 2/ Low K . 75C/W 3/ 1.4 Recommended operating conditions. 4/ AVDD+2.5 V AVSS-2.5 V DVDD. +3.3 V Operating temperature range (TA) . -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and
12、 functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ High K specifies values determined on a JESD 51-7
13、highly conductive printed circuit board. 3/ Low K specifies values determined on a JESD 51-3 low conductive printed circuit board. 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibili
14、ty or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09626 REV A PAGE 4 2. APPLICABLE DOCUMENTS EIA/JEDEC 51-
15、3 Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages EIA/JEDEC 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to th
16、e Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, o
17、r logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical perform
18、ance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Termin
19、al connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as shown in figure 3. 3.5.4 Timing waveforms. The timing waveforms shall be as shown in figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without licen
20、se from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09626 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max Analog multiplexer inputs section Absolute input volta
21、ge VINAIN0-AIN15, AINCOM with respect to DGND -55C to +125C 01 AVSS 100 mV AVDD+ 100 mV V -40C to +105C 02 AVSS 100 mV AVDD+ 100 mV On channel resistance RON-55C to +125C 01 80 typical -40C to +105C 02 80 typical Crosstalk CT fIN= 1 kHz -55C to +125C 01 -110 typical dB -40C to +105C 02 -110 typical
22、Sensor bias SBCS SBCS1:0 = 01 -55C to +125C 01 1.5 typical A (current source) -40C to +105C 02 1.5 typical SBCS1:0 = 11 -55C to +125C 01 24 typical -40C to +105C 02 24 typical 1.5 A:24 A ratio error RE -55C to +125C 01 1 typical % -40C to +105C 02 1 typical ADC input section Full scale input voltage
23、 VFSVIN= ADCINP ADCINN -55C to +125C 01 1.0 6 VREFtypical V -40C to +105C 02 1.0 6 VREFtypical Absolute input voltage VIN ADCINP, ADCINN -55C to +125C 01 AVSS 100 mV AVDD+ 100 mV V -40C to +105C 02 AVSS 100 mV AVDD+ 100 mV Differential input impedance ZDIN-55C to +125C 01 65 typical k -40C to +105C
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