DLA DSCC-DWG-V62 13615-2013 MICROCIRCUIT LINEAR LOW NOISE HIGH SPEED DIFFERENTIAL AMPLIFIER MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dl
2、a.mil/ Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, LINEAR, LOW NOISE, HIGH SPEED DIFFERENTIAL AMPLIFIER, MONOLITHIC SILICON 13-05-29 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/13615 REV PAGE 1 OF 17 AMSC N/A 5962-V058-13 Provided by IH
3、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13615 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low noise, high speed differenti
4、al amplifier microcircuit, with an operating temperature range of -55C to +105C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineerin
5、g documentation: V62/13615 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 ADA4930-1-EP Low noise, high speed differential amplifier 1.2.2 Case outline(s). The case outline(s) are as specif
6、ied herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 MO-220-WEED Lead frame chip scale 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold
7、 plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range (VS) 5.5 V Power dissipation (PD) at TA= +105C 550 mW Junction temperature range (TJ) 150C Storage temperature range (TSTG) . -65C to +125C Lead temperature (soldering, 10 seconds) . 300C 1.4 Reco
8、mmended operating conditions. 2/ Supply voltage range (VS) 3.3 V to 5 V Operating free-air temperature range (TA) . -55C to +105C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the d
9、evice at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Use of this product beyond the manufacturers design rules or stated parameters i
10、s done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO
11、. 16236 DWG NO. V62/13615 REV PAGE 3 1.5 Thermal characteristics. Thermal resistance, junction to ambient (JA) 81.6C/W 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed
12、 to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE c
13、ode, or logo B. Pin 1 identifier and H2X C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and elec
14、trical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1
15、. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13615 REV PAGE 4 TABLE I. Electrical pe
16、rformance characteristics. 1/ Test Symbol Conditions 2/ VS= 3.3 V, unless otherwise specifiedTemperature, TA Device type Limits Unit Min Max Dynamic performance. -3 dB small signal bandwidth SSBW VO,dm= 0.1 VP-P+25C 01 1430 typical MHz -3 dB large signal bandwidth LSBW VO,dm= 2 VP-P+25C 01 887 typic
17、al MHz Bandwidth for 0.1 dB flatness VO,dm= 0.1 VP-P+25C 01 380 typical MHz Slew rate SR VO,dm= 2 V step, 25% to 75% +25C 01 2877 typical V/s Settling time to 0.1% tSVO,dm= 2 V step, RL= 200 +25C 01 6.3 typical ns Overdrive recovery time G = 3, VIN,dm= 0.7 VP-Ppulse +25C 01 1.5 typical ns Noise / ha
18、rmonic performance. Second harmonic distortion HD2 VO,dm= 2 VP-P, fC= 10 MHz -55C to +105C 01 -98 typical dBc VO,dm= 2 VP-P, fC= 30 MHz -91 typical VO,dm= 2 VP-P, fC= 70 MHz -79 typical VO,dm= 2 VP-P, fC= 100 MHz -73 typical Third harmonic distortion HD3 VO,dm= 2 VP-P, fC= 10 MHz -55C to +105C 01 -9
19、7 typical dBc VO,dm= 2 VP-P, fC= 30 MHz -88 typical VO,dm= 2 VP-P, fC= 70 MHz -79 typical VO,dm= 2 VP-P, fC= 100 MHz -73 typical Third order intermodulation distortion (IMD) VO,dm= 1 VP-P/ tone, fC= 70.05 MHz 0.05 MHz +25C 01 91 typical dBc VO,dm= 1 VP-P/ tone, fC= 140.05 MHz 0.05 MHz 86 typical See
20、 footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13615 REV PAGE 5 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Condit
21、ions 2/ VS= 3.3 V, unless otherwise specifiedTemperature, TA Device type Limits Unit Min Max Noise / harmonic performance - continued. Input voltage noise f = 100 kHz +25C 01 1.15 typical nV / -55C to +105C 1.2 typical HzInput current noise f = 100 kHz +25C 01 3 typical pA / HzDC performance. Input
22、offset voltage VIOVIP= VIN= VOCM= 0 V, RL= open circuit -55C to +105C 01 -3.1 +3.1 mV Input offset voltage drift VIO-55C to +105C 01 2.75 typical V / C Input bias current IIB+25C 01 -36 -16 A Input bias current drift IIB-55C to +105C 01 -0.05 typical A / C Input offset current IIO +25C 01 -1.8 +1.8
23、A Open loop gain RF= RG= 10 k, VO= 0.5 V, +25C 01 64 typical dB RL= open circuit -55C to +105C 61 typical Input characteristics. Input common mode voltage range +25C 01 0.3 1.2 V Input resistance RIN Differential +25C 01 150 typical k Common mode 3 typical M See footnotes at end of table. Provided b
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