DLA DSCC-DWG-V62 13610-2013 MICROCIRCUIT LINEAR WIDEBAND LOW DISTORTION DIFFERENTIAL AMPLIFIER MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dl
2、a.mil/ Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, LINEAR, WIDEBAND, LOW DISTORTION, DIFFERENTIAL AMPLIFIER, MONOLITHIC SILICON 13-07-01 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/13610 REV PAGE 1 OF 17 AMSC N/A 5962-V048-13 Provided b
3、y IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13610 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance wideband, low distortion, di
4、fferential amplifier microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the en
5、gineering documentation: V62/13610 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 THS4500-EP Wideband, low distortion, differential amplifier 1.2.2 Case outline(s). The case outline(s) are
6、 as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 8 MO-187-AA-T Plastic small outline with thermal pad 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder d
7、ip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13610 REV PAGE 3 1.3 Absolute maximum ratings. 1/
8、 Supply voltage range (VS) 16.5 V Input voltage (VIN) VSOutput current (IOUT) . 150 mA 2/ Differential input voltage (VID) 4 V Maximum junction temperature range (TJ) . +150C 3/ Storage temperature range (TSTG) -65C to +150C Lead temperature, 1.6 mm (1/16 inch) from case for 10 seconds +300C Electro
9、static discharge (ESD): Human body model (HBM) . 4,000 V Charge device model (CDM) 1,000 V Machine model (MM) . 100 V 1.4 Recommended operating conditions. 4/ Supply voltage (VS) : Dual supply 5 V nominal and 7.5 V maximum Single supply 5 V minimum and 15 V maximum Operating junction temperature ran
10、ge (TJ) -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is no
11、t implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ This device may incorporate a thermal pad on the underside of the chip. This acts as a heat sink and must be connected to a thermally dissipative plane for proper power dissipation. Failur
12、e to do so, may result in exceeding the maximum junction temperature which could permanently damage the device. 3/ The absolute maximum temperature under any condition is limited by the constraints of the silicon process. 4/ Use of this product beyond the manufacturers design rules or stated paramet
13、ers is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDE
14、NT NO. 16236 DWG NO. V62/13610 REV PAGE 4 1.5 Thermal characteristics. Thermal metric Symbol Case X Unit Thermal resistance, junction-to-ambient 5/ JA63.1 C/W Thermal resistance, junction-to-case (top) 6/ JC(TOP)46.2 C/W Thermal resistance, junction-to-board 7/ JB33.9 C/W Characterization parameter,
15、 junction-to-top 8/ JT1.9 C/W Characterization parameter, junction-to-board 9/ JB33.6 C/W Thermal resistance, junction-to-case (bottom) 10/ JC(BOTTOM)11.9 C/W 5/ The thermal resistance, junction-to-ambient under natural convection is obtained in a simulation on a JEDEC standard, high-K board, as spe
16、cified in JESD51-7, in an environment described in JESD51-2a. 6/ The thermal resistance, junction-to-case (top) is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 7/ The therma
17、l resistance, junction-to-board is obtained by simulating in an environment with a ring cold plate fixture to control the printed circuit board (PCB) temperature, as described in JESD51-8. 8/ Characterization parameter, junction-to-top (JT) estimates the junction temperature of a device in a real sy
18、stem and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 9/ Characterization parameter, junction-to-board (JB) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining
19、JA, using a procedure described in JESD51-2a (sections 6 and 7). 10/ The thermal resistance, junction-to-case (bottom) is obtained by simulating a cold plate test on the exposed thermal pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88
20、. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13610 REV PAGE 5 2. APPLICABLE DOCUMENTS AMERICAN NATIONAL STANDARDS INSTITUTE ANSI SEMI STANDARD G30-88 - Test Method for
21、Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) J
22、EDEC Solid State Technology Association EIA/JESD 51-2a - Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) EIA/JESD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages EIA/JESD 51-8 - Integrated Circuits Thermal Test Met
23、hod Environment Conditions Junction-to-Board JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS
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