DLA DSCC-DWG-V62 13608-2013 MICROCIRCUIT LINEAR SINGLE CHANNEL HIGH SPEED LOW SIDE GATE DRIVER (WITH 4-A PEAK SOURCE AND 8-A PEAK SINK) MONOLITHIC SILICON.pdf
《DLA DSCC-DWG-V62 13608-2013 MICROCIRCUIT LINEAR SINGLE CHANNEL HIGH SPEED LOW SIDE GATE DRIVER (WITH 4-A PEAK SOURCE AND 8-A PEAK SINK) MONOLITHIC SILICON.pdf》由会员分享,可在线阅读,更多相关《DLA DSCC-DWG-V62 13608-2013 MICROCIRCUIT LINEAR SINGLE CHANNEL HIGH SPEED LOW SIDE GATE DRIVER (WITH 4-A PEAK SOURCE AND 8-A PEAK SINK) MONOLITHIC SILICON.pdf(12页珍藏版)》请在麦多课文档分享上搜索。
1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Origina
2、l date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, LINEAR, SINGLE CHANNEL HIGH SPEED, LOW SIDE GATE DRIVER (WITH 4-A PEAK SOURCE AND 8-A PEAK SINK), MONOLITHIC SILICON 13-06-06 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/13608 REV PAGE 1 OF 12 AMSC N/A 59
3、62-V065-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13608 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance single
4、channel high-speed, low side gat driver (with 4-A peak source and 8-A peak sink) microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an admi
5、nistrative control number for identifying the item on the engineering documentation: V62/13608 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 UCC27512-EP Single channel high-speed, low sid
6、e gat driver (with 4-A peak source and 8-A peak sink) 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins Package style X 6 Small Outline No-Lead 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device
7、 manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG N
8、O. V62/13608 REV PAGE 3 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range, (VDD) . -0.3 V to 20 V OUT voltage DC . -0.3 V to VDD+ 0.3 V Repetitive pulse less than 200 ns . -2.0 V to VDD+0.3 V 4/ Maximum output continuous current (OUTH source current and OUTL sink current): IOUT_DC(source)
9、0.3 A IOUT_DC(sink) 0.6 A Maximum output pulse current (0.5 s) (OUTH source current and OUTL sink current): IOUT_pulsed(source) 4 A IOUT_pulsed(sink) . 8 A IN+, IN- . -0.3 V to 20 V 5/ ESD: Human Body Model, HBM . 4000 V Charged Device Model, CDM . 1000 V Junction temperature range, TJ-55C to 150C S
10、torage temperature range -65C to 150C Lead temperature: Soldering, 10 sec 300C Reflow . 260C 1.4 Recommended operating conditions. 6/ Supply voltage range, (VDD) . 4.5 V to 18 V Operating junction temperature range -55C to 125C Input voltage, IN+ and IN- 0 V to 18 V _ 1/ Stresses beyond those listed
11、 under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditi
12、ons for extended periods may affect device reliability. 2/ All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See Packaging Section of the manufacturer datasheet for thermal limitations and considerations of packages. 3/ T
13、hese devices are sensitive to electrostatic discharge; follow proper device handling procedures. 4/ Values are verified by characterization on bench. 5/ Maximum voltage on input pins is not restricted by the voltage on the VDDpin. 6/ Use of this product beyond the manufacturers design rules or state
14、d parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A
15、 CODE IDENT NO. 16236 DWG NO. V62/13608 REV PAGE 4 1.5 Thermal characteristics. Thermal metric 7/ Case outline X Units Junction to ambient thermal resistance, JA8/ 85.6 C/W Junction to case (top) thermal resistance, JCtop9/ 100.1 Junction to board thermal resistance, JB10/ 58.6 Junction to top chara
16、cterization parameter, JT11/ 7.5 Junction to board characterization parameter, JB12/ 58.7 Junction to case (bottom) thermal resistance, JCbot13/ 23.7 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD51-2a Integrated Circuits Thermal Test Method Environment Conditions Natu
17、ral Convection (Still Air) JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages JESD51-8 Integrated Circuits Thermal Test Method Environment Conditions Junction-to-board (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid St
18、ate Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107). AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) STANDARD ANSI SEMI STANDARD G30-88 null Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be add
19、ressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org). 7/ For more information about traditional and new thermal metrics, see manufacturer data. 8/ The junction to
20、 ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K-board, as specified in JESD51-7, in an environment described in JESD51-2a. 9/ The junction to case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No
21、specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 10/ The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. 11/ The junc
22、tion to top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 12/ The junction to board characterization parameter, JB, estimates the
23、 junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 13/ The junction to case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No
24、specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13608 REV PAGE 5
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