ISO 6951-1986 Information processing Processor system bus interface (Eurobus A)《信息处理 处理机系统总线接口(欧洲总线A)》.pdf

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1、International Standard (! 6951 0 * (b) if communication with other buses is required, a bus link to each of the other buses. Figure 1 shows an example of a bus with a number of typical devices including an arbiter and a bus link. 0.4 Bus allocation. Information is transferred between devices on a ma

2、ster-and-slave basis. A device bids for control of the bus by means of its starred Request line and becomes the master device for that transfer after the arbiter has allocated the bus to it. This standard specifies the protocols by which devices bid for use of the bus and by which the arbiter alloca

3、tes the use of the bus to one of them. The standard does not, however, specify the algorithm used in making the selection, thus the system designer is given the choice of an allocation algorithm in order to optimize system performance. The protocol whereby a master device may flag an interrupt to th

4、e arbiter is also specified, but the subsequent action by the arbiter is left to the system designer to define. 0.5 Bus transfers. In addition to specifying the protocols for the execution of Read cycles (in which the master addresses a device as slave and reads data from it) and Write cycles (in wh

5、ich the master transfers data to the addressed slave), this standard also specifies the protocol for a Vector cycle in which an address, without data, is transferred from master to slave. ISO6961-1986(E) PROCESSOR Normally operates as Master device, but can act as Slave when in receipt of interrupts

6、. PROCESSOR As no one processor is deemed to be the Master device on the bus, several processors may be connected to the same bus. DMA-PERIPHERAL lNTERFACE CONTROLLER Controls the transfer of data to or from a user peripheral, performs DMA bus transfers as a Master device and receives control words

7、as a Slave. ARBITER Allocates use of the bus to requesting Master devices. - RECUEST LINES L BUS A MEMORY MEMORY MAPPED Blocks of memory are PERIPHERAL INTERFACE normally Slave devices. i.e. CONTROLLER they respond to transfers This Slave device controls initiated by other (Master) the activity of a

8、 user devices. peripheral. I I BUS LlNK Permits information to be transferred between the two buses to which it is connected. Figure 1. Eurobus with some typical devices The bus allocation protocols permit a master to hold the bus for repeated use without the need to make a fresh bid for every trans

9、fer, while also giving the arbiter the ability to instruct any master to release the bus for reallocation. A master is also permitted to retain the bus for an indivisible sequence of cycles, such as a Read- Modify-Write sequence. An additional protocol is defined whereby the arbiter may abort a cycl

10、e that is deemed to have failed. 0.6 Interbus transfers. The protocols for Read, Write and Vector cycles permit a master on bus A, for example, wishing to effect a transfer with a slave on bus B, to address a bus linker on bus A as slave. The bus linker then bids for use of bus B as master and addre

11、sses the required slave on bus B. Should master devices on both buses attempt simultaneous transfers, the bus link cannot become master on either bus and a condition of deadly embrace ensues. The Eurobus protocols permit the embrace to be broken simply. The protocols used by bus links to perform int

12、erbus addressing and data transfer are not within the scope of this standard. 0.7 Electrical requirements. The standard specifies the electrical and timing requirements that need to be obeyed by Eurobus A devices. Aspects covered within the electrical requirements include: (a) the voltage levels of

13、the active and quiescent logic states on the bus; (b) the required characteristics of the termination networks; 2 I I I BUS B (c) the required characteristics of the bus transmitters and receivers; (d) the required characteristics of the spurs to be connected to the bus. The specified set of electri

14、cal characteristics presupposes certain bus settling times for the transitions on the signal lines. Arising from these, certain timing constraints are specified. These constraints ensure that the relevant signal lines will have settled to the appropriate state before an associated control signal tra

15、nsition is issued. 0.8 Commercial and military versions. Two versions of Eurobus A are specified in this standard, a version for a commercial temperature range (0 “C to 70 “C) and a version for a military temperature range (-55 C to 125 “C). Where the requirements are different they are separately s

16、pecified for each version. 1. Scope and field of application This International Standard specifies a processor system bus interface known as Eurobus A (referred to in the following text as “the bus”) that is one of a family of in- terfaces for use in modular data acquisition, processing communicatio

17、n and control systems for military, industrial and other applications. NOTE 1. More detailed information about the requirements specified in this International Standard, including the data width and addressing capability, devices connected to the bus, bus allocation, bus transfers, interbus transfer

18、s and electrical re- quirements, and background information are given in clause 0. IS0 6951-1986 (El NOTE 2. In this International Standard, upper case letters are used for the first letter of names of bus cycles. NOTE 3. The titles of the publications referred to in this Inter- national Standard ar

19、e listed in annex P. 2. Definitions For the purposes of this International Standard the follow- ing definitions apply. 2.1 address. The location of a data word, or the value on the highway during the addressing phase of any Read, Write or Vector cycle. 2.2 arbiter. The device that performs the funct

20、ion of arbitration for the bus and is also responsible for servicing interrupts and for timing-out failed cycles and aborting them. 2.3 arbitration. The means whereby use of the bus is allocated to one of the bidding devices which then becomes the master. 2.4 backplane. The assembly of the bus with

21、connectors into which spur cards may be plugged. 2.5 bidding device. A device that wishes to initiate a cycle or group of cycles on a bus and that requests use of the bus. 2.6 bus. The complete set of bus lines used by a particular implementation of Eurobus. 2.7 bus cycle. A closed group of signals

22、on the bus that convey information between devices connected to it. This group consists of an addressing phase, in which the master places an address on the highway for recognition by a slave and, except in Vector cycles, a subsequent data transfer phase. 2.8 bus line. An electrical connection betwe

23、en two or more devices. 2.9 bus linker. A device that plugs into two or more buses thus providing a means whereby a master on one bus may transfer information to or from a slave on another bus. 2.10 bus voltage. The voltage on a bus line measured relative to the bus zero voltage reference. 2.11 byte

24、. A contiguous group of 8 bits. 2.12 circuit card. A card on which various electronic components are mounted and that plugs into a Eurobus backplane as a spur. 2.13 data. The information held at, written to, or read from an address. 2.14 deadly embrace. The conditions when two interbus transfers, us

25、ing the same bus linker, have been commenced and neither transfer can be completed. 2.15 device. A functional block, occupying one or more circuit cards, that communicates with other functional blocks by means of the bus or a subset of the bus. 2.16 extender panel. A circuit card that can be inserte

26、d between the bus and another circuit card to permit easy access to the latter while it is still connected to the bus. 2.17 Hold cycles. A sequence of cycles during which the master is not asked by the arbiter to release the bus for reallocation. 2.18 highway. Those bus lines used to convey data and

27、 addresses between devices on the Eurobus. 2.19 indivisible operation. A scqucnce of bus cycles for which the correct system function can only be guaranteed if no other bus cycles occur within that sequence, e.g. a Read-Modify-Write sequence. 2.20 interbus transfer. A transfer of information between

28、 devices that uses two or more buses and one or more bus linkers. 2.21 interrupt. A flag passed to the arbiter by a device in order to initiate a predetermined system-dependent function. 2.22 master. The device that initiates the transfer in question. 2.23 normal address space. An addressing space w

29、hose size is determined by the number of lines in the highway and that is addressable as words or bytes. 2.24 protocol. The signalling rules used to convey information or commands between devices connected to the bus. 2.25 pseudo address space. A second, independent addressing space whose size is de

30、termined by the number of lines in the highway and that is addressable as words only. 2.26 Read cycle. A bus cycle in which the master obtains a word or byte from the slave. 2.27 reset. The operation whereby each device connected to the bus is put into a predetermined initial condition. 2.28 Retain

31、cycle. A bus cycle at the end of which the master keeps control of the bus in order to complete an indivisible operation. 2.29 settling time. The time taken for a bus line to settle unambiguously into its new logical state from its previous state. 2.30 shelf. The physical structure that supports the

32、 backplane and the cards that plug into it. 2.31 skew. On the assumption that two logical transitions are launched simultaneously on two bus lines, the time difference between the receipt of those transitions at a given pair of receivers on a card connected to the bus at the point in question. 2.32

33、slave. The device that responds to the address placed on the bus by the master for the cycle in question. 2.33 spur. Device connected to the bus at some point between the two ends of the bus. 2.34 state (of a bus line). One of two conditions of a bus line, namely active or quiescent. 2.35 Vector cyc

34、le. A bus cycle in which the purpose is to pass an address from a master to a slave and in which no data transfer takes place. 2.36 word. A group of bits whose number corresponds to the maximum data width that can be conveyed over the bus in a single transfer. 2.37 0 V. The signal return path and, as such, the reference for all voltage measurements. NOTE. 0 V is not a safety earth. Where a safety earth is referred to in this standard, it is specifically identified. 2.38 Write cycle. A bus cycle in which a master writes a word or byte to a stave. 3