IEEE 1801-2015 en Design and Verification of Low-Power Energy-Aware Electronic Systems (IEEE Computer Society)《低功率 能量感知电子系统设计和验证(IEEE计算机协会)》.pdf

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1、 IEEE Standard for Design and Verification of Low-Power, Energy- Aware Electronic Systems Sponsored by the Design Automation Standards Committee IEEE 3 Park Avenue New York, NY 10016-5997 USA IEEE Computer Society IEEE Std 1801-2015 (Revision of IEEE Std 1801-2013) IEEE Std 1801-2015 (Revision of IE

2、EE Std 1801-2013) IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems Sponsor Design Automation Standards Committee of the IEEE Computer Society Approved 5 December 2015 IEEE-SA Standards Board Grateful acknowledgment is made to the following for permission to use

3、 source material: Accellera Systems Initiative Unified Power Format (UPF) Standard, Version 1.0 Cadence Design Systems, Inc. Library Cell Modeling Guide Using CPF Hierarchical Power Intent Modeling Guide Using CPF Silicon Integration Initiative, Inc. Si2 Common Power Format Specification, Version 2.

4、1 Abstract: A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power-management architecture, and for driving implementation of that power-management architecture. The method support

5、s incremental refinement of power-intent specifications required for IP-based design flows. Keywords: bottom-up implementation, buffers, energy-aware design, IEEE 1801, interface specification, IP reuse, isolation, level-shifting, power domains, power intent, power modeling, power states, successive

6、 refinement, supply states, repeaters, retention, Unified Power Format (UPF) The Institute of Electrical and Electronics Engineers, Inc. 3 Park Avenue, New York, NY 10016-5997, USA Copyright 2016 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Published 25 March 2

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35、ent rights, and the risk of infringement of such rights, is entirely their own responsibility. Further information may be obtained from the IEEE Standards Association. Copyright 2016 IEEE. All rights reserved. vi Participants At the time this IEEE standard was completed, the P1801 Working Group had

36、the following membership: John Biggs, Chair Erich Marschner, Vice Chair Sushma Honnavara-Prasad, Secretary Houssam Abbas Paul Bailey Guillaume Boillet Conor Byrne Louis Cardillo Shir-Shen Chang David Cheng Cyril Chevalier Ashley Crawford John Decker Stephan Diestelhorst Shaun Durnan Paul Floyd Jerry

37、 Frenkil Alan Gibbons Josefina Hobbs Anand Iyer Fred Jen Tim Jordan Sylvian Kaiser James Kehoe Tim Kogel Rick Koster Shaji Kunjumohamed Kaowen Liu Debajani Majhi Ilija Materic Gene Matter Jon McDonald Don Mills Kevin Nesmith Lawrence Neukom David Peterson Shreedhar Ramachandra Judith Richardson Fred

38、eric Saint-Preux Rich Scales Guido Schlothane Krishna Sekar Desinghu Pundi Srinivasan Amit Srivastava James Su Haruyuki Tago Ajay Thiriveedhi Venki Venkatesh Vita Vishnyakov Jon Worthington Vojin Zivojnovic The following members of the entity balloting committee voted on this standard. Balloters may

39、 have voted for approval, disapproval, or abstention. Accellera Organization, Inc. Advanced Micro Devices (AMD) ALDEC, Inc. ARM, Ltd. Broadcom Corporation Cadence Design Systems, Inc. Google Intel Corporation Japan Electronics and Information Technology Industries Association (JEITA) Marvell Semicon

40、ductor, Inc. MediaTek, Inc. Mentor Graphics Micron Technology, Inc. Microsoft Corporation NVIDIA Corporation PMC-Sierra, Inc. Qualcomm, Inc. Silicon Integration Initiative, Inc. STMicroelectronics Synopsys, Inc. Verific Design Automation, Inc.When the IEEE-SA Standards Board approved this standard o

41、n 8 December 2015, it had the following membership: John D. Kulick, Chair Jon Walter Rosdahl, Vice Chair Richard H. Hulett, Past Chair Konstantinos Karachalios, Secretary Masayuki Ariyoshi Ted Burse Stephen Dukes Jean-Philippe Faure J. Travis Griffith Gary Hoffman Michael Janezic Joseph L. Koepfinge

42、r* David J. Law Hung Ling Andrew Myles T. W. Olsen Glenn Parsons Ronald C. Petersen Annette D. Reilly Stephen J. Shellhammer Adrian P. Stephens Yatin Trivedi Philip Winston Don Wright Yu Yuan Daidi Zhong *Member Emeritus Copyright 2016 IEEE. All rights reserved. vii Introduction This introduction is

43、 not part of IEEE Std 1801-2015, IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems. The purpose of this standard is to provide portable, low-power design specifications that can be used with a variety of commercial products throughout an electronic system design

44、, analysis, verification, and implementation flow. When the electronic design automation (EDA) industry began creating standards for use in specifying, simulating, and implementing functional specifications of digital electronic circuits in the 1980s, the primary design constraint was the transistor

45、 area necessary to implement the required functionality in the prevailing process technology at that time. Power considerations were simple and easily assumed for the design as power consumption was not a major consideration and most chips operated on a single voltage for all functionality. Therefor

46、e, hardware description languages (HDLs) such as VHDL (IEC 61691-1-1/ IEEE Std 1076a)and SystemVerilog (IEEE Std 1800b) provided a rich set of capabilities necessary for capturing the functional specification of electronic systems, but no capabilities for capturing the power architecture (how each e

47、lement of the system is to be powered). As the process technology for manufacturing electronic circuits continued to advance, power (as a design constraint) continually increased in importance. Even above the 90 nm process node size, dynamic power consumption became an important design constraint as

48、 the functional size of designs increased power consumption at the same time battery-operated mobile systems, such as cell phones and laptop computers, became a significant driver of the electronics industry. Techniques for reducing dynamic power consumptionthe amount of power consumed to transition

49、 a node from a 0 to 1 state or vice versabecame commonplace. Although these techniques affected the design methodology, the changes were relatively easy to accommodate within the existing HDL-based design flow, as these techniques were primarily focused on managing the clocking for the design (more clock domains operating at different frequencies and gating of clocks when logic in a clock domain is not needed for the active operational mode). Multi-voltage power-management methods were also developed. These methods did not directly impact the functionality of the design, re