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1、 IEEE Standard for SystemVerilog Unified Hardware Design, Specification, and Verification Language Sponsored by the Design Automation Standards Committee IEEE 3 Park Avenue New York, NY 10016-5997 USA 21 February 2013 IEEE Computer Society and the IEEE Standards Association Corporate Advisory Group

2、IEEE Std 1800-2012 (Revision of IEEE Std 1800-2009) IEEE Std 1800-2012(Revision ofIEEE Std 1800-2009)IEEE Standard for SystemVerilogUnified Hardware Design, Specification, and Verification LanguageSponsorDesign Automation Standards Committeeof theIEEE Computer Societyand theIEEE Standards Associatio

3、n Corporate Advisory GroupApproved 5 December 2012IEEE-SA Standards BoardThe Institute of Electrical and Electronics Engineers, Inc.3 Park Avenue, New York, NY 10016-5997, USACopyright 2013 by The Institute of Electrical and Electronics Engineers, Inc.All rights reserved. Published 21 February 2013.

4、 Printed in the United States of America.IEEE, 802, and POSIX are registered trademarks in the U.S. Patent +1 978 750 8400. Permission to photocopy portions of any individual standard for educationalclassroom use can also be obtained through the Copyright Clearance Center.ivCopyright 2013 IEEE. All

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11、isit IEEE-SA Website at http:/standards.ieee.org/index.html.ErrataErrata, if any, for this and all other standards can be accessed at the following URL: http:/standards.ieee.org/findstds/errata/index.html. Users are encouraged to check this URL for errataperiodically.PatentsAttention is called to th

12、e possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken by the IEEE with respect to theexistence or validity of any patent rights in connection therewith. If a patent holder or patent applican

13、t hasfiled a statement of assurance via an Accepted Letter of Assurance, then the statement is listed on the IEEE-SA Website at http:/standards.ieee.org/about/sasb/patcom/patents.html. Letters of Assurance may indicatewhether the Submitter is willing or unwilling to grant licenses under patent right

14、s without compensation orunder reasonable rates, with reasonable terms and conditions that are demonstrably free of any unfairdiscrimination to applicants desiring to obtain such licenses.vCopyright 2013 IEEE. All rights reserved.Essential Patent Claims may exist for which a Letter of Assurance has

15、not been received. The IEEE is notresponsible for identifying Essential Patent Claims for which a license may be required, for conductinginquiries into the legal validity or scope of Patents Claims, or determining whether any licensing terms orconditions provided in connection with submission of a L

16、etter of Assurance, if any, or in any licensingagreements are reasonable or non-discriminatory. Users of this standard are expressly advised thatdetermination of the validity of any patent rights, and the risk of infringement of such rights, is entirely theirown responsibility. Further information m

17、ay be obtained from the IEEE Standards Association.viCopyright 2013 IEEE. All rights reserved.ParticipantsThe SystemVerilog Language Working Group is entity based. At the time this standard was completed,the SystemVerilog Working Group had the following membership: Karen Pieper, Accellera Representa

18、tive, Tabula, Inc., Chair Neil Korpusik, Oracle Corporation, Vice Chair, Technical Chair Dennis Brophy, Mentor Graphics Corporation, Secretary Stuart Sutherland, Sutherland HDL, Inc., Technical Editor Work on this standard was divided among primary committees. The Champions Committee was responsible

19、 for ensuring consistency in the work done by each committee.Neil Korpusik, Oracle Corporation, Chair Dave Rich, Mentor Graphics Corporation, Co-ChairThe Basic/Design Committee (SV-BC) was responsible for the specification of the design features ofSystemVerilog. Matt Maidment, Intel Corporation, Cha

20、ir Brad Pierce, Synopsys, Inc., Co-Chair Shalom Bresticker, Intel CorporationCharles Dawson, Cadence Design Systems, Inc.Josef Derner, Mentor Graphics CorporationJohn Goodenough, ARM, Ltd.Kaiming Ho, Fraunhofer IISHaim Kerem, Intel CorporationDmitry Korchemny, Intel CorporationDave Rich, Mentor Grap

21、hics CorporationNeil Sensarkar, Marvell Technology Group Ltd.Yatin Trivedi, Synopsys, Inc.Tony Tsai, Cisco Systems, Inc.Shalom Bresticker, Intel CorporationSurrendra Dudani, Synopsys, Inc. Francoise Martinolle, Cadence Design Systems, Inc. Brad Pierce, Synopsys, Inc. Stuart Sutherland, Sutherland HD

22、L, Inc. Tom Alsop, Intel CorporationShalom Bresticker, Intel CorporationEric Coffin, Mentor Graphics CorporationPeter Flake, Accellera Systems InitiativeAlex Gran, Mentor Graphics CorporationMark Hartoog, Synopsys, Inc.Kaiming Ho, Fraunhofer IIS Francoise Martinolle, Cadence Design Systems, Inc.Dave

23、 Rich, Mentor Graphics CorporationArnab Saha, Mentor Graphics CorporationDaniel Schostak, ARM, Ltd.Steven Sharp, Cadence Design Systems, Inc.Stuart Sutherland, Sutherland HDL, Inc.Gordon Vreugdenhil, Mentor Graphics CorporationviiCopyright 2013 IEEE. All rights reserved.The Enhancement Committee (SV

24、-EC) was responsible for the specification of the testbench features ofSystemVerilog. Mehdi Mohtashemi, Synopsys, Inc., Chair Neil Korpusik, Oracle Corporation, Co-Chair The Assertions Committee (SV-AC) was responsible for the specification of the assertion features ofSystemVerilog. Dmitry Korchemny

25、, Intel Corporation, Chair Tom Thatcher, Oracle Corporation, Co-Chair The C API Committee (SV-CC) was responsible for on the specification of the DPI, the SystemVerilogVerification Procedural Interface (VPI), and the additional coverage API. Charles Dawson, Cadence Design Systems, Inc., Chair Ghassa

26、n Khoory, Synopsys, Inc., Co-Chair The Discrete Committee (SV-DC) was responsible for defining features to support modeling of analog/mixed-signal circuit components in the discrete domain.Scott Little, Intel Corporation, Chair Abhijeet Kolpekwar, Cadence Design Systems, Inc., Co-Chair Tom Alsop, In

27、tel CorporationJonathan Bromley, Accellera Systems InitiativeDhiraj Goswami, Synopsys, Inc.Alex Gran, Mentor Graphics CorporationMark Hartoog, Synopsys, Inc.Scott Little, Intel CorporationFrancoise Martinolle, Cadence Design Systems, Inc.Dave Rich, Mentor Graphics CorporationRay Ryan, Mentor Graphic

28、s CorporationArturo Salz, Synopsys, Inc.Daniel Schostak, ARM Ltd.Nilotpal Sensarkar, Marvell Technology Group, Ltd.Steven Sharp, Cadence Design Systems, Inc.Brandon Tipp, Intel CorporationTony Tsai, Cisco Systems, Inc.Gordon Vreugdenhil, Mentor Graphics CorporationAshok Bhatt, Cadence Design Systems

29、, Inc.Laurence Bisht, Intel CorporationEduard Cerny, Synopsys, Inc.Ben Cohen, Accellera Systems InitiativeDana Fisman, Synopsys, Inc.John Havlicek, Freescale, Inc.Tapan Kapoor, Cadence Design Systems, Inc.Jacob Katz, Intel CorporationManisha Kulshrestha, Mentor Graphics CorporationScott Little, Inte

30、l CorporationAnupam Prabhakar, Mentor Graphics CorporationErik Seligman, Intel CorporationSamik Sengupta, Synopsys, Inc.Chuck Berking, Cadence Design Systems, Inc.Steve Dovich, Cadence Design Systems, Inc.Amit Kohli, Cadence Design Systems, Inc.Francoise Martinolle, Cadence Design Systems, Inc.Abiga

31、il Moorhouse, Mentor Graphics CorporationMichael Rohleder, Freescale, Inc.Arnab Saha, Mentor Graphics CorporationArturo Salz, Synopsys, Inc.George Scott, Mentor Graphics CorporationBassam Tabbara, Synopsys, Inc.Jim Vellenga, Cadence Design Systems, Inc.Vitaly Yankelevich, Cadence Design Systems, Inc

32、.Shekar Chetput, Cadence Design Systems, Inc.Scott Cranston, Cadence Design Systems, Inc.Dave Cronauer, Synopsys, Inc.Mark Hartoog, Synopsys, Inc.John Havlicek, Freescale, Inc.Ghassan Khoory, Synopsys, Inc.Francoise Martinolle, Cadence Design Systems, Inc.Arturo Salz, Synopsys, Inc.Sundaram Sangames

33、waran, Texas Instruments, Inc.Steven Sharp, Cadence Design Systems, Inc.Gordon Vreugdenhil, Mentor Graphics CorporationIan Wilson, Accellera Systems InitiativeviiiCopyright 2013 IEEE. All rights reserved.The following members of the entity balloting committee voted on this standard. Balloters may ha

34、ve votedfor approval, disapproval, or abstention.When the IEEE-SA Standards Board approved this standard on 5 December 2012, it had the followingmembership:Richard H. Hulett, ChairJohn Kulick, Vice ChairRobert M. Grow, Past ChairKonstantinos Karachalios, Secretary*Member EmeritusAlso included are th

35、e following nonvoting IEEE-SA Standards Board liaisons:Richard DeBlasio, DOE RepresentativeMichael Janezic, NIST RepresentativeMatthew J. CegliaIEEE Manager, Professional ServicesMichelle TurnerIEEE Standards Program Manager, Document DevelopmentJoan WooleryIEEE Standards Program Manager, Technical

36、Program DevelopmentAccellera Systems InitiativeCadence Design Systems, Inc.Fraunhofer IISFreescale, Inc.Intel CorporationJapan Electronics and Information TechnologyIndustries Association (JEITA)Marvell Technology Group Ltd.Mentor Graphics CorporationOracle CorporationSynopsys, Inc.Satish AggarwalMa

37、sayuki AriyoshiPeter BalmaWilliam BartleyTed BurseClint ChaplinWael DiabJean-Philippe FaureAlexander GelmanPaul HouzJim HughesYoung Kyun KimJoseph L. Koepfinger*David J. LawThomas LeeHung LingOleg LogvinovTed OlsenGary RobinsonJon Walter RosdahlMike SeavyYatin TrivediPhil WinstonYu YuanixCopyright 2

38、013 IEEE. All rights reserved.IntroductionThe purpose of this standard is to provide the electronic design automation (EDA), semiconductor, andsystem design communities with a well-defined and official IEEE unified hardware design, specification,and verification standard language. The language is de

39、signed to coexist and enhance the hardwaredescription and verification languages (HDVLs) presently used by designers while providing the capabilitieslacking in those languages. SystemVerilog is a unified hardware design, specification, and verification language based on the AccelleraSystemVerilog 3.

40、1a extensions to the Verilog hardware description language (HDL) B3, published in2004.aAccellera is a consortium of EDA, semiconductor, and system companies. IEEE Std 1800 enables aproductivity boost in design and validation and covers design, simulation, validation, and formal assertion-based verif

41、ication flows. SystemVerilog enables the use of a unified language for abstract and detailed specification of the design,specification of assertions, coverage, and testbench verification based on manual or automaticmethodologies. SystemVerilog offers application programming interfaces (APIs) for cov

42、erage andassertions, and a direct programming interface (DPI) to access proprietary functionality. SystemVerilogoffers methods that allow designers to continue to use present design languages when necessary to leverageexisting designs and intellectual property (IP). This standardization project will

43、 provide the VLSI designengineers with a well-defined IEEE standard, which meets their requirements in design and validation, andwhich enables a step function increase in their productivity. This standardization project will also providethe EDA industry with a standard to which they can adhere and t

44、hat they can support in order to deliver theirsolutions in this area.aThe numbers in brackets correspond to those of the bibliography in Annex Q.This introduction is not part of IEEE Std 1800-2012, IEEE Standard for SystemVerilogUnified Hardware Design,Specification, and Verification Language.xCopyr

45、ight 2013 IEEE. All rights reserved.xiCopyright 2013 IEEE. All rights reserved.ContentsPart One: Design and Verification Constructs1. Overview 21.1 Scope 21.2 Purpose. 21.3 Content summary. 21.4 Special terms 31.5 Conventions used in this standard . 31.6 Syntactic description 41.7 Use of color in th

46、is standard 51.8 Contents of this standard 51.9 Deprecated clauses. 81.10 Examples 81.11 Prerequisites. 82. Normative references. 93. Design and verification building blocks 113.1 General. 113.2 Design elements. 113.3 Modules . 113.4 Programs 123.5 Interfaces 133.6 Checkers. 143.7 Primitives . 143.8

47、 Subroutines 143.9 Packages. 143.10 Configurations . 153.11 Overview of hierarchy . 153.12 Compilation and elaboration 163.13 Name spaces 183.14 Simulation time units and precision. 194. Scheduling semantics. 234.1 General. 234.2 Execution of a hardware model and its verification environment . 234.3

48、 Event simulation 234.4 Stratified event scheduler. 244.5 SystemVerilog simulation reference algorithm . 294.6 Determinism. 294.7 Nondeterminism. 304.8 Race conditions 304.9 Scheduling implication of assignments . 304.10 PLI callback control points 325. Lexical conventions . 335.1 General. 335.2 Lex

49、ical tokens 335.3 White space 33xiiCopyright 2013 IEEE. All rights reserved.5.4 Comments 335.5 Operators 335.6 Identifiers, keywords, and system names 345.7 Numbers. 355.8 Time literals . 405.9 String literals 405.10 Structure literals. 425.11 Array literals 435.12 Attributes . 435.13 Built-in methods 456. Data types 476.1 General. 476.2 Data types and data objects 476.3 Value set 476.4 Singular and aggregate types .486.5 Nets and variables 496.6 Net types 506.7 Net declarations . 616.8 Variable declarations . 646.9 Vector declarations 666.10 Implicit declaratio