IEEE 1450 1-2005 en Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450-1999) for Semiconductor Design Environments (IEEE Computer Society)《半导体.pdf

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1、IEEE Std 1450.1-20051450.1TMIEEE Standard for Extensions toStandard Test Interface Language (STIL)(IEEE Std 14501999) for SemiconductorDesign Environments3 Park Avenue, New York, NY 10016-5997, USAIEEE Computer SocietySponsored by theTest Technology Standards Committee30 September 2005Print: SH95344

2、PDF: SS95344IEEE Std 1450.1-2005(R2011) IEEE Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450TM-1999) for Semiconductor Design Environments Sponsor Test Technology Standards Committee of the IEEE Computer Society Approved 9 June 2005 Reaffirmed 16 June 2011 IEEE-SA S

3、tandards BoardApproved 17 November 2005Reaffirmed 25 July 2012American National Standards InstituteAbstract: Standard Test Interface Language (STIL) provides an interface between digital test generation tools and test equipment. Extensions to the test interface language (contained in this standard)

4、are defined that (1) facilitate the use of the language in the design environment and (2) facilitate the use of the language for large designs encompassing subdesigns with reusable patterns. Keywords: advanced scan architecture, core, environment, fail feedback, lockstep, parallel patterns, paramete

5、rized data, pattern tiling, pragma, signal variable, system on chip (SoC), test protocol The Institute of Electrical and Electronics Engineers, Inc. 3 Park Avenue, New York, NY 10016-5997, USA Copyright 2005 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Publishe

6、d 30 September 2005. Printed in the United States of America. IEEE is a registered trademark in the U.S. Patent +1 978 750 8400. Permission to photocopy portions of any individual standard for educational classroom use can also be obtained through the Copyright Clearance Center. Copyright 2005 IEEE.

7、 All rights reserved. iiiIntroductionThe Standard Test Interface Language (STIL) was initially developed by an ad hoc consortium of automatictest equipment vendors (ATE), electronic design automation vendors (EDA), and integrated circuit (IC)manufacturers to address the lack of a common solution for

8、 transferring digital test data from the generationenvironment to the test equipment.The scope of the initial STIL standard was limited to satisfy the basic needs of pattern definition. Additionalcapabilities are developed as separate projects resulting in separate (dot) extensions to the initial ST

9、ILstandard. The scope of this extension is defined in 1.1 and is primarily to address design needs.Whereas the initial STIL standard was developed by reviewing many languages already in existence in theindustry, this standard has been developed by inventing new capabilities in support of new device

10、designs.The new language constructs have been added such that they do not alter in any way the initial definition ofSTIL, yet are syntactically compatible with the initial STIL language.Much of the work to develop and validate these extensions has been done by prototyping on the part of thecontribut

11、ing companies.Notice to usersErrataErrata, if any, for this and all other standards can be accessed at the following URL: http:/standards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL forerrata periodically.InterpretationsCurrent interpretations can be acces

12、sed at the following URL: http:/standards.ieee.org/reading/ieee/interp/index.html.PatentsAttention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with respect to the ex

13、istence orvalidity of any patent rights in connection therewith. The IEEE shall not be responsible for identifyingpatents or patent applications for which a license may be required to implement an IEEE standard or forconducting inquiries into the legal validity or scope of those patents that are bro

14、ught to its attention.This introduction is not part of IEEE Std 1450.1-2005, IEEE Standard for Extensions to Standard Test InterfaceLanguage (STIL) (IEEE Std 1450-1999) for Semiconductor Design Environments.iv Copyright 2005 IEEE. All rights reserved.ParticipantsAt the time this standard was complet

15、ed, the 1450.1 Working Group had the following membership:Tony Taylor, ChairGreg Maston, Vice ChairThe following members of the individual balloting committee voted on this standard. Balloters may havevoted for approval, disapproval, or abstention. When the IEEE-SA Standards Board approved this stan

16、dard on 9 June 2005, it had the followingmembership:Steve M. Mills, ChairRichard H. Hulett, Vice ChairDon Wright, Past ChairJudith Gorman, Secretary*Member EmeritusAlso included are the following nonvoting IEEE-SA Standards Board liaisons:Satish K. Aggarwal, NRC RepresentativeRichard DeBlasio, DOE R

17、epresentativeAlan Cookson, NIST RepresentativeMichelle TurnerIEEE Standards Project EditorTom BartensteinJohn CosleyDaniel FanBruce KaufmanJose SantiagoDouglas SpraguePeter WohlChris BaggeBritt BrooksDwayne BurekKeith ChowAntonio M. CicuLuis CordovaJohn CosleyFrans De JongPeter DecherJason DoegeDave

18、 DowdingGeir EideDaniel FanRandall GrovesWilliam HannaPeter HarrodJim HeatonRohit KapurBruce KaufmanJames KemerlingAdam LeyMaurice LousbergGregory LuriYuhai MaKevin MarquessDenis MartinGreg MastonGary MichelYinghua MinJames MonzelZainalabedin NavabiCharles NgetheJim OReillyDon OrganSerafin A. Perez-

19、LopezVikram PunjMike RicchettiGordon RobinsonJames RuggieriJose SantiagoGil ShultzDouglas SpragueTony TaylorScott ValcourtSrinivasa VemuruGregg WilderPeter WohlMark D. BowmanDennis B. BrophyJoseph BruderRichard CoxBob DavisJulian Forster*Joanna N. GueninMark S. HalpinRaymond HapemanWilliam B. HopfLo

20、well G. JohnsonHermann KochJoseph L. Koepfinger*David J. LawDaleep C. MohlaPaul NikolichT. W. OlsenGlenn ParsonsRonald C. PetersenGary S. RobinsonFrank StoneMalcolm V. ThadenRichard L. TowsendJoe D. WatsonHoward L. WolfmanCopyright 2005 IEEE. All rights reserved. vContents1. Overview 11.1 Scope 21.2

21、 Purpose. 32. Definitions, acronyms, and abbreviations 32.1 Definitions . 32.2 Acronyms and abbreviations . 43. Structure of this standard . 44. STIL syntax description. 54.1 Reserved words 54.2 Reserved characters . 64.3 Reserved UserFunctions 74.4 Signal and group name characteristics. 84.5 STIL n

22、ame spaces and name resolution 85. Expressions 95.1 Constant and variable expressions . 95.2 Expression delimiterssingle quotes and parentheses . 95.3 Arithmetic expressionsinteger, real, time, boolean 115.4 Pattern data expressions. 125.5 Expression processing 145.6 Booleanboolean_expr 185.7 Intege

23、rsinteger_expr 185.8 Logic expressionslogic_expr .195.9 Real expressionsreal_expr . 205.10 Addition to timing expressionstime_expr 215.11 SignalVariablessigvar_expr . 225.12 Formal parameters in procedures and macros . 245.13 Integer listsinteger_list. 246. Statement structure and organization of ST

24、IL information . 257. STIL statement. 257.1 STIL syntax 267.2 STIL example 268. UserKeywords statement . 268.1 UserKeywords syntax 268.2 UserKeywords example. 26vi Copyright 2005 IEEE. All rights reserved.9. Variables block 279.1 Variables block syntax. 279.2 Variables example 299.3 Variables scopin

25、g. 299.4 Variables synchronizing 3110. Signals block 3210.1 Signals block syntax 3310.2 Signals example . 3310.3 Bracketed signal notation enhancement 3411. SignalGroups block 3511.1 SignalGroups syntax 3511.2 SignalGroups, WFCMap, and Variables example. 3511.3 Default WFCMap attribute value 3611.4

26、Defining indexed signal groups . 3612. PatternBurst block 3712.1 PatternBurst syntax 3712.2 PatternBurst example. 3912.3 Tiling and synchronization of patterns 4012.4 If and While statements . 4213. Timing block and WaveformTable block 4313.1 Additional domain specification 4313.2 CompareSubstitute

27、operations, S. 4314. ScanStructures block 4414.1 ScanStructures syntax 4414.2 Scan cell namingcell_ref, chain_ref, cell_group, chain_group . 4714.3 Scoping rules for ScanStructure blocks . 4814.4 Example indexed list of scan cells . 4914.5 Example of ScanChainGroups and ActiveScanChain . 4914.6 Scan

28、 chain segments and cell groups.5115. Pattern data 5215.1 Data content read backC, D, E, S, U, W . 5315.2 Vector data mapping and joiningm, j 5515.3 Specifying event data in a patterne.5715.4 Using expressions within pattern data .5816. Pattern statements 5916.1 Additional Pattern syntax. 5916.2 Vec

29、tor data constraintsF, E 6116.3 Shift and LoopData statements 6216.4 Loop statement using an integer expression 6416.5 MergedScan function. 65Copyright 2005 IEEE. All rights reserved. vii17. Procedure and macro data substitution 6517.1 Nested procedure and macro cells . 6517.2 Passing parameters to

30、variables . 6617.3 Default value of formal parameters . 6717.4 Data substitution using WFCConstant and SignalVariable. 6718. Environment block. 6918.1 Environment syntax . 6918.2 MAP_STRING syntax. 7118.3 NameMaps example 7118.4 Compact scan-cell mapping using InheritNameMap. 7319. Pragma block . 74

31、19.1 Pragma syntax 7420. PatternFailReport . 7420.1 PatternFailReport syntax 7520.2 PatternFailReport example 76Annex A (informative) Glossary . 78Annex B (informative) Signal mapping using SignalVariables. 79Annex C (informative) Using logic expression with signals . 83Annex D (informative) Using b

32、oolean expressions in patterns.84Annex E (informative) Variables and expressions in algorithmic patterns 85Annex F (informative) Using AllowInterleave 87Annex G (informative) Vector data mapping using m 90Annex H (informative) Vector data joining using j 93Annex I (informative) Block data collection

33、 . 96Annex J (informative) Using Fixed and Equivalent statements 98Annex K (informative) Independent parallel patterns . 100Annex L (informative) Applications using new ScanStructures syntax 102Annex M (informative) BreakPoints using MergedScan() function 106Annex N (informative) Labels and X statem

34、ents for diagnostic feedback 109Annex O (informative) Use of STIL.1 for specific applications . 112Annex P (informative) Bibliography . 114Copyright 2005 IEEE. All rights reserved. 1IEEE Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450TM-1999) for Semiconductor Desig

35、n Environments1. OverviewSTIL is an evolving standard being developed in support of various needs for interfacing between testgeneration tools and test equipment. IEEE Std 1450-1999 (STIL.0) B31forms the basis for this evolution.New “dot” standards (like this one) are being developed to address spec

36、ific needs beyond STIL.0.This (STIL.1) standard addresses design-related aspects of digital test data. This standard can also be viewedas the addition of advanced features to the STIL.0 baseline to allow for the usage of STIL in more complexapplications, while leaving the basic standard unchanged as

37、 a vehicle for transmitting basic test data. Thefollowing is a brief overview of the new features in STIL.1 to support advanced applications such as(1) embedded cores,2(2) families of test patterns, (3) mapping to automated test equipment (ATE) systems,3(4) mapping to simulation, and (5) devices wit

38、h advanced design for test (DFT). Please see Annex O for alist of specific statements for each of these features.Environment mapping: Data for a device exist in many forms and in many other software environments.Examples include (1) simulation environment, (2) static analysis environment, (3) specif

39、ic ATE systemenvironment. The STIL Environment block is a new mechanism to relate STIL data to these otherenvironments. No assumptions, expectations, or limitations are imposed on the other environments. It is justa way of relating one to the other.Parameterized data: Much of STIL data are declarati

40、ve in nature (i.e., it defines various static attributes of adevice or pattern set). The addition of constant declarations, IntegerConstant and WFCConstant, allows adata set to be created that applies to a family of devices.Complex test protocol definition: Test protocol definitions are usually cont

41、ained in STIL procedures orMacroDefs and are used to specify the application of a series of data values to a device. STIL.0 supportsscan chain data passing and simple WaveformCharacter (WFC) data passing via the # and % characters.STIL.1 enhances this capability by allowing the use of data substitut

42、ion from SignalVariables and integer-1The numbers in brackets correspond to those of the bibliography in Annex P.2This standard contains syntax in support of embedded cores. See IEEE Std 1450.6TM-2005 (Core Test Language) B5 for the complete specification.3This standard contains syntax in support of

43、 ATE systems. See IEEE P1450.3TM(Test Resource Constraints) B4 for the complete specification.IEEEStd 1450.1-2005 IEEE STANDARD FOR EXTENSIONS TO STIL (IEEE STD 1450-1999)2 Copyright 2005 IEEE. All rights reserved.Complex test protocol definition: Test protocol definitions are usually contained in S

44、TIL procedures orMacroDefs and are used to specify the application of a series of data values to a device. STIL.0 supportsscan chain data passing and simple WaveformCharacter (WFC) data passing via the # and % characters.STIL.1 enhances this capability by allowing the use of data substitution from S

45、ignalVariables and integer-expressions. STIL.1 also enhances the functionality of Loops and Vectors and adds If/While decisions onpattern statements. These capabilities are needed for BIST, embedded cores, and various test accessmechanisms.Advanced scan architecture: Advanced DFT techniques require

46、additional capabilities beyond what isdefined in STIL.0, which includes multistate scan cells, reconfigurable scan-chains, and scan-chainindexing.Run-time pattern decisions: The If, Else, While, and LoopData are new STIL.1 constructs that have beenadded for specification of pattern activity. These s

47、tatements are needed in the specification of patterns to berun in the simulation environment. Although there is no standardization among ATE systems on run-timeinstructions for pattern execution, it is anticipated that restricted versions of these statements will beincorporated into ATE test pattern

48、s. Pattern burst options: New variations on the PatternBurst have been added to allow for patterns running inparallel, patterns running in LockStep, and patterns that can be reordered. For parallel pattern execution, thespecification for how the patterns fit together can be specified with the Fixed

49、and Extend statements.Enhanced user extensibility: The UserKeyword extensibility defined in STIL.0 has been extended to allowkeywords to be defined on a per-block-type basis.Signal relationships: Additional syntax is provided to allow the specification of relationships betweensignals. This process is preformed via m to map WFCs to another WFC, j to join WFCs, Extend to definebehavior of signals beyond the bounds of a given pattern, and Fixed to restrict any further changes to signalswithin a pattern.Fail feedback: Three new features are a