REG NASA-LLIS-0824-2000 Lessons Learned Space Radiation Effects on Electronic Components in Low-Earth Orbit.pdf

《REG NASA-LLIS-0824-2000 Lessons Learned Space Radiation Effects on Electronic Components in Low-Earth Orbit.pdf》由会员分享，可在线阅读，更多相关《REG NASA-LLIS-0824-2000 Lessons Learned Space Radiation Effects on Electronic Components in Low-Earth Orbit.pdf（8页珍藏版）》请在麦多课文档分享上搜索。

1、Best Practices Entry: Best Practice Info:a71 Committee Approval Date: 2000-04-18a71 Center Point of Contact: JSCa71 Submitted by: Wil HarkinsSubject: Space Radiation Effects on Electronic Components in Low-Earth Orbit Practice: During system design, choose electronic components/devices which will pr

2、ovide maximum failure tolerance from Space Radiation Effects. The information above provides guidance in selection of radiation hardened (rad-hard) solid state devices and microcircuits for use in space vehicles which operate in low-earth orbits.Programs that Certify Usage: This practice has been us

3、ed on Space Shuttle Orbiter.Center to Contact for Information: JSCImplementation Method: This Lesson Learned is based on Reliability Practice No. PD-ED-1258; from NASA Technical Memorandum 4322A, NASA Reliability Preferred Practices for Design and Test.Benefit:This practice provides enhanced reliabi

4、lity and availability as well as improved chances for mission success. Failure rates due to space radiation effects will be significantly lower, and thus system down time will be much lower, saving program cost and resources.Implementation Method:Provided by IHSNot for ResaleNo reproduction or netwo

5、rking permitted without license from IHS-,-,-Space Radiation Environment, Essential Basics: Radiation in space is generated by particles emitted from a variety of sources both within and beyond our solar system. Radiation effects from these particles can not only cause degradation, but can also caus

6、e failure of the electronic and electrical systems in space vehicles or satellites. Even high altitude commercial airliners flying polar routes have shown documented cases of avionics malfunctions due to radiation events.Primary Cosmic rays interact with gaseous and other matter at high altitudes an

7、d produce secondary radiation. The combination of both contributes to the Space Radiation environment. The fusion process on the Suns interior produces electrons and protons in great abundance along with helium and other heavier nuclei, which travel towards earth as the solar wind. This solar wind r

8、adiates out from the sun in all directions; but the flux of these particles varies with sunspot activity and solar flares. In addition to the particles originating from the sun are particles from other stars and heavy ion sources such as novas and supernovas in our galaxy and beyond. In interplaneta

9、ry space these ionizing particles constitute the major radiation threat. These particles are influenced by planetary or earths magnetic field to form radiation belts, which in earths case are known as Van Allen Radiation belts, containing trapped electrons in the outer belt and protons in the inner

10、belt. The composition and intensity of the radiation varies significantly with the trajectory of a space vehicle.Experience with many spacecraft since Explorer I shows that higher electron concentrations are observed between 45 degrees and 85 degrees latitude in both the northern and southern hemi-s

11、pheres, indicating that the belts descend to a lower altitude in these regions. For low inclination orbits, less than 30 degrees, the electron concentrations are relatively low. Due to the earths asymmetric magnetic field, a region in the Atlantic near Argentina and Brazil, known as South Atlantic A

12、nomaly (SAA), has relatively high concentrations of electrons. The SAA is known to cause problems such as: single event upsets (SEU) in altimeter electronics gate arrays, and “hard“ SEUs in the Space Shuttle Orbiters Star Trackers Analog-to-Digital converter. The March 1991 solar storms significantl

13、y increased the charged particle distributions in the Van Allen belts, also creating a third belt.In addition to the trapped charged particles in Van Allen radiation belts (electrons and protons), the spacecraft experience radiation threats from high energy heavy ions in space called Galactic Cosmic

14、 rays, and secondary X-Rays or Bremstrahlung generated by particles penetrating the skin of the space-craft while they lose energy. This type of electromagnetic radiation is a significant percentage of the total component producing total dose effects. The usual (Centimeter Gram Second) unit used to

15、specify radiation dose or deposited energy is the “rad,“ which is defined as 100 ergs/gm of material. The material is always specified in parentheses, e.g., rad(Si). But the International system of units (SI) defines an essentially Meter Kilogram Second (MKS) units for absorbed dose called the “gray

16、“ (GY). One GY is defined as the deposition of 1 joule per kilogram of radiation energy, i.e 1GY = 100 rads.Solar Flares also contribute varying quantities of electrons, protons, and lower energy heavy ions. Solar flares occur randomly at different times, and during times of high solar activity may

17、contribute Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-very high fluxes of particles over periods of hours or days. Heavy ions of various energies cause single event effects (SEE). A convenient way to express the transient charge generated by the

18、se heavy ions or charged particles is in charge per unit length, e.g. pC/micron. However a more frequently used term (but less intuitive) to express the same thing is called, “Linear Energy Transfer or LET“, which is expressed in MeV.cm2/mg.In bit-storage devices the high energy heavy-ions cause bit

19、s to change, and are expressed in terms of bit error rates or SEU Error Probability. The SEU Error Probability is a number generated by computer from three data inputs: (a) the expected distribution of particles vs. LET, (b) the device cross-section for upset or latch up as function of LET, usually

20、obtained from laboratory measurements, and (c) a calculation of expected error rate that combines the first two relationships with a calculation of the effect of the omni-directional particle flux on the charge produced in the device by the incident particles. Computer programs are available that pe

21、rform this calculation. The net result is a fixed number for the upset or latch up probability. The following rules must be observed for estimating total dose environments:Criteria for Selection of Parts for Enhanced Reliability:a. For Space vehicles or satellites in low inclination ( 28 degrees) Lo

22、w Earth Orbit (LEO), 85 degrees) LEO in both northern and southern hemispheres, typical dose rates due to increased number of trapped electrons are 1000-10,000 rad(Si)/year.There are three categories of components having the following characteristics:1. Commercial: a72 Process and Design limit the r

23、adiation hardnessa72 No lot radiation controlsa72 Hardness levels: a73 Total Dose: 2 to 10 krad (typical)a73 SEU Threshold LET: 5 Mev/mg/cm2a73 SEU Error Rate: 10-5errors/bit-day (typical)a72 Customer performs rad testing, and assumes all riska72 Customer evaluation and risk2. Rad Tolerant: a72 Desi

24、gn assures rad hardness up to a certain levela72 No lot radiation controlsa72 Hardness levels: a73 Total Dose: 20 to 50 krad (typical)a73 SEU Threshold LET: 20 MeV/mg/cm2Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-a73 SEU Error Rate: 10-7- 10-8er

25、rors/bit-daya72 Usually tested for functional fail only, riskya72 Customer evaluation and risk3. Rad Hard: a72 Designed and processed for particular hardness levela72 Wafer lot radiation testeda72 Hardness levels:a72 Total Dose: 200 krad to 1 Mrada72 SEU Threshold LET: 80-150 MeV/mg/cm2a72 SEU Error

26、 Rate: 10-10- to 10-12errors/bit-day4. Latch up:5. None present in Silicon-on-Insulator/Silicon on Sapphire (SOI/SOS) Complimentary Metal Oxide Semiconductor (CMOS)- technologies Exhibit Low SEU sensitivity for SEEsNOTE: Although Class S does not guarantee that the parts are rad-hard, the design pro

27、cess does dictate whether a part is rad-tolerant or not.Using rad-soft components does not significantly reduce cost, but greatly increases risk. There are no components that are ideal for all parameters. IC design requires many tradeoffs in performance (cost included as performance parameter). Comm

28、ercial components are useful only for commercial applications, where low cost, latest technology (even if it is immature), and high speed takes precedence over extreme temperatures and voltage ranges. Shielding these devices in Space Applications is a futile effort, especially for Single Event Effec

29、ts such as SEU and Single Event Latch up (SEL).Total Dose Hardness Levels of Various Technologies: It should be noted that Bipolar device operation depends upon minority carrier current levels flowing through the substrate, while Metal Oxide Semiconductor (MOS) technologies operate upon majority car

30、rier current flows at the surface of the substrate. (Junction Field Effect Transistors depend upon majority carrier currents through the substrate). This is what makes their interaction with radiation different . Table 1 shows a comparison of Bipolar to MOS devices and radiation hardness.Provided by

31、 IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-refer to D descriptionD Table 1: Radiation Hardness Comparison NOTE: Achieving total dose hardness in CMOS-SOS is more difficult than in bulk CMOS, but SOS does appear to offer advantages relative to dose rate, wi

32、th respect to SEE.Silicon BIPOLAR technology is also heavily utilized in Linear devices, but analog devices require different transistor design characteristics from logic devices whose operation involves simple switching of logic states. Linear devices are affected by radiation in two ways.1. Low cu

33、rrent transistor betas (current-gains) are degraded by surface effects similar to those which degrade MOS devices. Collector current (i.e. base current minus base-emitter leakage current times the beta of the transistor), is thus affected as a result of radiation exposure. When the leakage current (

34、base-to-emitter) increases significantly as a result of radiation, the transistor will not function properly at low current levels, causing problems with input impedance, input offset and open loop gains.2. Bipolar devices (Integrated Circuits) often contain parasitic MOS devices, which present no p

35、roblem in logic devices. Bipolar logic circuits typically operate at 5V with logic thresholds below 2V also helps. The parasitics typically have turn-on voltages in excess of 30V. Bipolar linear devices, however, typically operate at higher voltages (with positive- to-negative supply differentials o

36、f from 30V to 40V, making them more susceptible to even small radiation induced shifts in the turn-on voltages of parasitics). The problem is partially solved by design layout changes.Other processing characteristics such as the difference between silicon dioxide and silicon nitride (used for surfac

37、e passivation) can also change the radiation tolerance characteristics of bipolar linear Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-devices. With improvements in current technology, most such devices are rad-hard to one mega-Rad(si) level. One m

38、ethod to compensate for the transistor-to-transistor leakage current effects due to radiation is corrected by using dielectric isolation technique in bipolar devices.Total Ionizing Dose (TID) Effects in CMOS Devices: CMOS-Bulk Devices (ICs) experience “latch up“ due to a parasitic four-layer PNPN pa

39、th, inherent in most unhardened devices. These parasitic four-layer devices act like a Silicon Control Rectifier (SCR), which once latched cannot be turned off without shutting off the power. Radiation hardening for total dose of such devices can be achieved by choice of technology and design change

40、s to minimize the formation of such paths within an Integrated circuit. CMOS-SOS or CMOS-SOI devices do not have such paths and are inherently rad-hard up to one megaRad(Si), but are comparatively more expensive. CMOS-Bulk devices can be made rad-hard by introducing epitaxial layers to reduce the fo

41、rmation of PNPN paths, thus reducing the chances for latch up to one mega-Rad (Si).Single Event Effects (SEE): High energy protons or heavy ions lose their energy mainly through ionization, i.e create electron-hole pairs as they traverse through p-n junctions or the depth of penetration in the semic

42、onductor material. Some of the deposited charge recombines, and some is collected at the junction contacts. The net effect is a very short duration pulse of current that induces transient at internal circuit nodes. The magnitude of the charge, which is generally much larger for ions with high atomic

43、 numbers, depends on the energy and ion type, as well as the path length over which the charge is collected. The effect of these random charges on the circuit depends on a number of factors, including the minimum charge required to switch a digital circuit state, called SEUs. Single bit upsets are e

44、asy to correct by Error Correction Codes but multiple bit corrections may lead to problems, and can be corrected by redundancy, etc. Also, memory devices are hardened by design to minimize single event upsets. CMOS Static Random Access Memory (SRAM) cells can be hardened by adding capacitors, resist

45、ors, transistors or combination of these devices to the circuit, at the cost of circuit parameter degradation especially the speed.If the CMOS-bulk process creates parasitic SCRs or PNPN structures, the excessive charge may cause a Latch up, leading to a SEL, which can sometimes lead to the destruct

46、ion of the device. It can be minimized by choice of rad-hard process or technologies. CMOS-SOS/CMOS-SOI, Bipolar and GaAs devices are not prone to latch up or SEL.Latch-up in rad-hard devices is minimized through design and process using (a) numerous, regularly spaced well and substrate contacts in

47、design, (b) thin-epi/shallow well CMOS processes, and (c) butting of the source-to-substrate and source-to-well contacts. The only certain way to eliminate latch up is to use CMOS-SOS or CMOS-SOI process that eliminates one of the parasitic transistors, thereby removing the possibility of latch up.T

48、he problems resulting from SELs are either immediate or latent damage which may reduce functional performance. Non rad-hard circuits or devices can incur damage from excessively high currents within a few microseconds. Once latch-up occurs, a device would remain in a high current, Provided by IHSNot

49、 for ResaleNo reproduction or networking permitted without license from IHS-,-,-latched condition until power is turned off. Power cycling will be required each time latch up occurs, which will temporarily shutdown sections of the subsystem that share power supplies. Along with power cycling, circuits and subsystems affected by any component will have to be