JEDEC JESD8-14A 01-2007 1 0 V + - 0 1 V (Normal Range) and 0 7 V - 1 1 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuits (Min.pdf
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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD8-14A.01SEPTEMBER 2007JEDECSTANDARD1.0 V +/- 0.1 V (Normal Range) and 0.7 V - 1.1 V (Wide Range) Power SupplyVoltage and Interface Standard for Nonterminated Digital Integrated Circuits(Minor revision of JES8-14A, November 2005)NOTICEJEDEC standards and pu
2、blications contain material that has been prepared, reviewed, and approvedthrough the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel.JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufact
3、urers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purchaser in selecting and obtaining with minimum delay theproper product for use by those other than JEDEC members, whether the standard is to be used eitherdomestically or internationally.JEDEC stan
4、dards and publications are adopted without regard to whether or not their adoption mayinvolve patents or articles, materials, or processes. By such action JEDEC does not assume any liability toany patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards orpubl
5、ications.The information included in JEDEC standards and publications represents a sound approach to productspecification and application, principally from the solid state device manufacturer viewpoint. Within the No claims to be in conformance with this standard may be made unless all requirements
6、stated in thestandard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication shouldbe addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA22201-3834, (703)907-7559 or www.jedec.org.Published byJEDEC Solid Stat
7、e Technology Association 20072500 Wilson BoulevardArlington, VA 22201-3834This documentmay be downloaded free of charge, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material.Price: Please refer to the
8、current Catalog of JEDEC Engineering Standards and Publications oat www.jedec.orgPrinted in the U.S.A.All rights reservedPLEASE! DONT VIOLATE THE LAW ! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited numbe
9、r of copies through entering into a license agreem ent. For inform ation, contact: JEDEC Solid State Technology Association 2500 W ilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 8-14A.01Page 11.0 V +/- 0.1 V (NORMAL RANGE) AND 0.7 V - 1.1 V (WIDE RANGE) POWE
10、R SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS(From JEDEC Board Ballot JCB-01-102 and JCB-05-81, formulated under the cognizance of the JC-16 Committee on Interface Technology.)1 ScopeThis standard defines power supply voltage ranges, dc interface and switching
11、 parameters for a high speed, low voltage family of nonterminated digital circuits driving/driven by parts of the same family, or mixed families which comply with the input receiver specifications. The specifications in this standard represent a minimum set of interface specifications for CMOS compa
12、tible circuits.The purpose of this standard is to provide a standard of specification for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. Clause 2.3 describes normal dc electrical characteristics and clause 2.4 (added in revision A
13、) describes the optional chracteristics for Schmitt trigger operation.2 Standard specificationsAll voltages are referenced to ground except where noted.2.1 Absolute maximum continuous ratingsNOTE 1 Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Expo
14、sure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum conditions is not implied.NOTE 2 Not to exceed 1.4 V.NOTE 3 The maximum voltage allowed between any two signal (input, output or input/output) pins or an
15、y signal pin and VDDmust be less than 1.6 V.Supply Voltage, VDD-0.4 V to 1.4 Vdc Input Voltage, VIN(except I/O pins) (note 1, 2 and 3) -0.4 V to VDD+ 0.4 Vdc Output Voltage, VOUT(including I/O pins) (note 2 and 3) -0.4 V to VDD+ 0.4 Vdc Input Diode Current, IIK(VIVDD) +/- 20 mAdc Output Diode Curren
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