JEDEC JESD79F-2010 DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION.pdf

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1、JESD79FPage 1DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION16 M X4 (4 M X4 X4 banks), 8 M X8 (2 M X8 X4 banks), 4 M X16 (1 M X16 X4 banks)32 M X4 (8 M X4 X4 banks), 16 M X8 (4 M X8 X4 banks), 8 M X16 (2 M X16 X4 banks)64MX4(16MX4X4banks),32MX8(8MX8X4banks),16MX16(4MX16X4banks)128MX4(32MX4X4banks),64MX8(

2、16MX8X4banks),32MX16(8MX16X4banks)256 M X4 (64 M X4 X4 banks), 128 M X8 (32 M X8 X4 banks), 64 M X16 (16 M X16 X4 banks)FEATURESDouble-data-ratearchitecture;twodatatransfersper clock cycleBidirectional, datastrobe(DQS) istransmitted/re-ceived with data, to be used in capturing data atthe receiver DQ

3、S is edge-aligned with data for READs; cen-ter-aligned with data for WRITEs Differential clock inputs (CK and CK)DLLalignsDQandDQStransitionswithCKtransi-tions Commands entered on each positive CK edge;data and data mask referenced to both edges ofDQS Four internal banks for concurrent operation Dat

4、a mask (DM) for write data Burst lengths: 2, 4, or 8 CAS Latency:2 or 2.5, DDR400 also includesCL = 3AUTOPRECHARGEoptionforeachburstaccess Auto Refresh and Self Refresh Modes 2.5 V (SSTL_2 compatible) I/O VDDQ:+2.5 V 0.2 V for DDR 200, 266, or 333+2.6 0.1 V for DDR 400 VDD:+3.3 V 0.3 V or +2.5 V 0.2

5、V for DDR 200, 266,or 333+2.6 0.1 V for DDR 400GENERAL DESCRIPTIONThe DDR SDRAM is a high-speed CMOS, dynamicrandom-access memory internally configured as aquad-bank DRAM. These devices contain thefollow-ing number of bits:64 Mb has 67,108,864 bits128 Mb has 134,217,728 bits256 Mb has 268,435,456 bi

6、ts512 Mb has 536,870,912 bits1 Gb has 1,073,741,824 bitsTheDDRSDRAMusesadouble-data-ratearchitec-ture to achieve high-speed operation. The doubledataratearchitectureisessentiallya2nprefetcharchi-tecture with an interface designed to transfer two datawords per clock cycle at the I/O pins. A single re

7、ad orwrite access for the DDR SDRAM effectively consistsofasingle2n-bitwide,oneclockcycledatatransferatthe internal DRAM core and two corresponding n-bitwide, one-half-clock-cycle data transfers at the I/Opins.A bidirectional data strobe (DQS) is transmitted ex-ternally, along with data, for use in

8、data capture at thereceiver. DQS is a strobe transmitted by the DDRSDRAM during READs and by the memory controllerduring WRITEs. DQS is edge-aligned with data forREADs and center-aligned with data for WRITEs.The DDR SDRAM operates from a differential clock(CK and CK; the crossing of CK going HIGH an

9、d CKgoing LOW will be referred to as the positive edge ofCK).Commands(addressandcontrolsignals)arereg-isteredateverypositiveedgeofCK.Inputdataisregis-tered on both edges of DQS, and output data is refer-enced to both edges of DQS, as well as to both edgesof CK.Read and write accesses to the DDR SDRA

10、M areburst oriented; accesses start at a selected locationandcontinueforaprogrammednumberof locationsina programmed sequence. Accesses begin with theregistrationofanACTIVEcommand, whichis thenfol-lowed by a READ or WRITE command. The addressbits registered coincident with the ACTIVE commandare used

11、to select the bank and row to be accessed.The address bits registered coincident with the READor WRITE command are used to select the bank andthestartingcolumnlocationfortheburstaccess.The DDR SDRAM provides for programmable reador write burst lengths of 2, 4 or 8 locations. An AUTOPRECHARGE functio

12、n may be enabled to provide aself-timed row precharge that is initiated at the end ofthe burst access.As with standard SDRAMs, the pipelined, multibankarchitecture of DDR SDRAMs allows for concurrentoperation, thereby providing high effective bandwidthby hiding row precharge and activation time.An a

13、uto refresh mode is provided, along with a pow-er-saving, power-down mode. All inputs are compat-ible with the JEDEC Standard for SSTL_2. All outputsare SSTL_2, Class II compatible.InitialdevicesmayhaveaVDDsupplyof3.3V(nomi-nal). Eventually, all devices will migrate to a VDD sup-plyof2.5V(nominal).D

14、uringthisinitialperiod ofprod-uct availability, this split will be vendor and devicespecific.This data sheet includes all features and functional-ity required for JEDEC DDR devices; options not re-quired, but listed, are noted as such. Certain vendorsmayelecttoofferasupersetofthisspecificationbyof-f

15、ering improved timing and/or including optional fea-tures. Users benefit fromknowing thatany systemde-sign based on the required aspects of thisspecification are supported by all DDR SDRAM ven-dors; conversely, users seeking to use any supersetspecifications bear the responsibility to verify support

16、with individual vendors.Note:Thefunctionalitydescribed in,and thetim-ing specifications included in this data sheet arefor the DLL Enabled mode of operation.Note: This specification defines the minimum set of requirements for JEDEC X4/X8/X16 DDR SDRAMs.Vendors will provide individual data sheets in

17、their specific format. Vendor data sheets should be con-sulted for optional features or superset specifications.JESD79FPage 2CONTENTSFeatures 1.General Description 1Pin Assignment Diagram, TSOP2 Package 3Address Assignment Table 1a TSOP2 Package 3.Pin Assignment Diagram, BGA Package 4.Address Assign

18、ment Table 1b BGA Package 5.Functional Block Diagram - X4/X8/X16 5Pin Descriptions, Table 2 6Functional Description 7Initialization 7.Register Definition 7.Mode Register 7.Burst Length 8Table 3, Burst Definition 8.Fig. 4, Mode Register Definition 8Burst Type 9Read Latency 9.Operating Mode 9.Terminol

19、ogy DefinitionsDDR200 9.DDR266 9.DDR333 9.DDR400 9.Fig. 5, Required CAS Latencies 10.Extended Mode Register 11DLL Enable/Disable 11Output Drive Strength 11Fig.6, Extended Mode Register Definitions 11.Commands 12Truth Table 1a (Commands) 12Truth Table 1b (DM Operation) 12Truth Table 2 (CKE) 13.Truth

20、Table 3 (Current State, Same Bank) 14 it doesnot represent an actual circuit implementation.Note 2: DM is a unidirectional signal (input only) but is internally loaded to match the load of the bidirectional DQ and DQS signals.Note 3: Not all address inputs are used on all densities.COMMANDDECODEX4 X

21、8 X16X 8 16 32Y4 816JESD79FPage 6TABLE 2: PIN DESCRIPTIONSSYMBOL TYPE DESCRIPTIONCK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signalsare sampled on the crossing of the positive edge of CK and negative edge of CK.Output (read) data is referenced to the cr

22、ossings of CK and CK (both directions ofcrossing).CKE(CKE0)(CKE1)Input Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock sig-nals, and device input buffers and output drivers. Taking CKE LOW provides PRE-CHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or AC-TIVE

23、 POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for POW-ER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous forSELF REFRESH exit, and for output disable. CKE must be maintained highthroughout READ and WRITE accesses. Input buffers, excluding CK, CK and CKEare disabled du

24、ring POWER-DOWN. Input buffers, excluding CKE are disabledduring SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOWlevel after Vdd is applied upon 1st power up. After VREF has become stable duringthe power on and initialization sequence, it must be maintained for proper operationof

25、the CKE receiver. For proper self-refresh entry and exit, VREF must be main-tained to this input The standard pinout includes one CKE pin. Optional pinouts in-clude CKE0 and CKE1 on different pins, to facilitate device stacking.CS(CS0)(CS1)Input Chip Select: All commands are masked when CS is regist

26、ered high. CS providesfor external bank selection on systems with multiple banks. CS is considered part ofthe command code. The standard pinout includes one CS pin. Optional pinoutsinclude CS0 and CS1 on different pins, to facilitate device stacking.RAS,CAS,WEInput Command Inputs: RAS,CASand WE (alo

27、ng with CS) define the command beingentered.DM(LDM)(UDM)Input Input Data Mask: DM is an input mask signal for write data. Input data is maskedwhen DM is sampled HIGH along with that input data during a WRITE access. DMis sampled on both edges of DQS. Although DM pins are input only, the DM loadingma

28、tches the DQ and DQS loading. For the X16, LDM corresponds to the data onDQ0-DQ7; UDM corresponds to the data on DQ8-DQ15. DM may be driven high,low, or floating during READs.BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ,WRITE or PRECHARGE command is being appl

29、ied.A0-A13 Input Address Inputs: Provide the row address for ACTIVE commands, and the columnaddress and AUTO PRECHARGE bit for READ/WRITE commands, to select onelocation out of the memory array in the respective bank. A10 is sampled during aprecharge command to determine whether the PRECHARGE applie

30、s to one bank(A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bankis selected by BA0, BA1. The address inputs also provide the op-code during aMODE REGISTER SET command. BA0 and BA1 define which mode register isloaded during the MODE REGISTER SET command (MRS or EMRS). A1

31、2 is usedon device densities of 256Mb and above; A13 is used on device densities of 1Gb.DQ I/O Data Bus: Input/Output.DQS(LDQS)(UDQS)I/O Data Strobe: Output with read data, input with write data. Edge-aligned with readdata, centered in write data. Used to capture write data. For the X16, LDQS corre-

32、sponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15.NC No Connect: No internal electrical connection is present.VDDQ Supply DQ Power Supply: +2.5 V 0.2 V. for DDR 200, 266, or 333+2.6 0.1 V for DDR 400VSSQ Supply DQ Ground.VDD Supply Power Supply: One of +3.3 V 0.3 V or +2.5 V 0.

33、2 V for DDR 200, 266, or 333+2.6 0.1 V for DDR 400VSS Supply Ground.VREF Input SSTL_2 reference voltage.JESD79FPage 7FUNCTIONAL DESCRIPTIONThe DDR SDRAM is a high-speed CMOS, dy-namic random-access memory internally config-ured as a quad-bank DRAM. These devices con-tain the following number of bits

34、:64Mb has 67,108,864 bits128Mb has 134,217,728 bits256Mb has 268,435,456 bits512Mb has 536,870,912 bits1Gb has 1,073,741,824 bitsTheDDRSDRAMusesadouble-data-ratearchi-tecture to achieve high-speed operation. Thedouble-data-rate architecture is essentially a 2nprefetch architecture, with an interface

35、 designed totransfer two data words per clock cycle at the I/Opins. A single read or write access for the DDRSDRAM consists of a single 2n-bit wide, one clockcycle data transfer at the internal DRAM core andtwo corresponding n-bit wide, one-half clock cycledatatransfers at theI/O pins. DQ, DQS, acce

36、ssesstart ataselectedlocationandcontinueforaprogrammednumberoflocationsin a programmed sequence. Accesses begin withthe registration of an ACTIVE command, which isthenfollowedby aREADorWRITE command.Theaddress bits registered coincident with theACTIVEcommandareusedtoselect thebank androwtobeaccessed

37、 (BA0, BA1 select the bank; A0-A13 se-lecttherow).TheaddressbitsregisteredcoincidentwiththeREADor WRITEcommandareusedtose-lect the starting column location for the burst ac-cess.Prior to normal operation, the DDR SDRAM mustbe initialized. The following sections provide de-tailedinformationcoveringde

38、viceinitialization,reg-ister definition, command descriptions and deviceoperation.INITIALIZATIONDDRSDRAMsmustbepoweredupandinitializedin a predefined manner. Operational proceduresother than those specified may result in undefinedoperation. Nopower sequencingis specifiedduringpower upandpower down g

39、iventhe followingcrite-ria:D VDD and VDDQ are drivenfrom asingle powerconverter output, ANDD VTT is limited to 1.35 V, ANDD VREF tracks VDDQ/2OR, the following relationships must be followed:D VDDQ is driven after or with VDD such thatVDDQ VDD + 0.3 V ANDD VTT is driven after or with VDDQ such thatV

40、TT VDDQ + 0.3 V, ANDD VREF is driven after or with VDDQ such thatVREF VDDQ + 0.3 V.At least one of these two conditions must be met.Except for CKE, inputs are not recognized as validuntilafterVREFisapplied.CKEisanSSTL_2input,but will detect an LVCMOS LOW level after VDD isapplied. Maintaining an LVC

41、MOS LOW level onCKE during power-up is requiredto guaranteethattheDQandDQSoutputswillbeintheHigh-Zstate,where they will remain until driven in normal opera-tion (by a read access). After all power supply andreference voltages are stable, and the clock isstable, the DDR SDRAM requires a 200 s delaypr

42、ior to applying an executable command.Once the 200 s delay has been satisfied, a DE-SELECT or NOP command should be applied, andCKE should be brought HIGH. Following the NOPcommand, a PRECHARGE ALL command shouldbe applied. Next a MODE REGISTER SET com-mandshouldbeissuedfortheExtendedModeReg-ister,

43、to enable the DLL, then a MODE REGISTERSET commandshouldbeissuedfor theModeReg-ister,toresettheDLL,andtoprogramtheoperatingparameters. 200clock cycles arerequiredbetweenthe DLL reset and any executable command. APRECHARGE ALL command should be applied,placing the device in the ”all banks idle” state

44、.Once in the idle state, two AUTO refresh cyclesmust be performed. Additionally, a MODE REG-ISTER SET command for the Mode Register, withthereset DLLbit deactivated(i.e., toprogram oper-ating parameters without resetting the DLL) mustbe performed. Following these cycles, the DDRSDRAM is ready for no

45、rmal operation.REGISTER DEFINITIONMODE REGISTERThe Mode Register is used to define the specificmodeof operation of the DDRSDRAM. This defini-tion includes the selection of a burst length, a bursttype, a CAS latency, and an operating mode, asshown in Figure NO TAG. The Mode Register isprogrammed via

46、the MODE REGISTER SET com-mand(withBA0= 0andBA1= 0) andwillretainthestored information until it is programmed again orthe device loses power (except for bit A8, whichmay be self-clearing).Mode Register bits A0-A2 specify the burstlength, A3 specifies the type of burst (sequential orinterleaved), A4-

47、A6 specify the CAS latency, andA7-A13or(A12on256Mb/512Mb,A13on1Gbseefigure 4) specify the operating mode.JESD79FPage 8The Mode Register must be loaded when allbanksareidleandnoburstsareinprogress,andthecontrollermust waitthespecifiedtimebeforeinitiat-ing any subsequent operation. Violating either of

48、these requirements will result in unspecifiedopera-tion.Burst LengthReadandwriteaccesses totheDDRSDRAMareburst oriented, withtheburst lengthbeingprogram-mable, as shown in Figure NO TAG. The burstlength determines the maximum number of columnlocations that canbeaccessedfor agivenREADorWRITE command.

49、 Burst lengths of 2, 4, or 8 loca-tionsareavailableforboththesequentialandthein-terleaved burst types.Table 3BURST DEFINITIONReserved states shouldnot beused, as unknownoperation or incompatibility with future versionsmay result.When a READ or WRITE command is issued, ablock of columns equal to the burst length is effec-tively selected. All accesses for that burst takeplace within this block, meaning that the burst willwrap within the block if a boundary is reached. Theblock is uniquely selected by A1-Ai when the