JEDEC JESD60A-2004 A Procedure for Measuring P-Channel MOSFET Hot-Carrier- Induced Degradation Under DC Stress《P路MOSFET热载波的测量规程 导致DC压下的退化》.pdf

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1、JEDEC STANDARD A Procedure for Measuring P-Channel MOSFET Hot-Carrier-Induced Degradation Under DC Stress JESD60A (Revision of JESD60) SEPTEMBER 2004 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved throu

2、gh the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvem

3、ent of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether o

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6、dard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or

7、www.jedec.org Published by JEDEC Solid State Technology Association 2004 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the

8、 resulting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced wi

9、thout permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 6

10、0A -i- A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION UNDER DC STRESS CONTENTS Page Introduction iii 1 Scope 1 2 Applicable standards 1 3 Terms and definitions 2 4 Technical requirements 5 4.1 Equipment requirements 5 4.2 Test structure requirements 5 4.3 Measurement requ

11、irements 5 5 The hot-carrier stress test procedures 6 5.1 Determining stress bias conditions 7 5.2 Test devices 9 5.3 Initial characterization 9 5.4 Stress cycle 9 5.5 Interim characterization 9 5.6 Stress termination 10 6 Data analysis 10 7 Precautions 11 7.1 Test sample 11 7.2 Stress 12 7.3 Interi

12、m measurements 12 7.4 Data analysis 12 8 Required reporting 12 8.1 Test transistor identification 12 8.2 VDD, VBB13 8.3 MOSFET channel length and width 13 8.4 VDSat stress, VBS at stress, VGSat stress 13 8.5 Initial IGand IBand IDat stress 13 8.6 Initial ID(lin), gm(max), VT(ci), VT(ext), ID(sat), I

13、D(leak)13 8.7 tTARfor ID(lin) , gm(max), VT(ci), VT(ext), ID(sat), ID(leak)8.8 Total test time 13 8.9 Measurement temperature 13 8.10 Linear drain voltage VDS(lin)13 JEDEC Standard No. 60A -ii- JEDEC Standard No. 60A -iii- Introduction Hot-carrier-induced change of MOSFET parameters over time is an

14、important reliability concern in modern microcircuits. High-energy carriers, also called hot carriers, are generated in the MOSFET by the large channel electric fields near the drain region. These hot carriers transfer energy to the lattice through phonon emission and break bonds at the Si/SiO2inter

15、face. The electric fields accelerate locally the carriers to effective temperatures well above the lattice temperature. Carriers also are injected into the SiO2and can be trapped there. The trapping or bond breaking creates oxide charge and interface traps that affect the channel carrier mobility an

16、d the effective channel potential. In this document we will describe a procedure to characterize the hot-carrier-induced degradation of P-MOSFETs during channel conduction (i.e., VGS 0 V, VDS 0 V). In the case of p-channel devices, electrons, generated by impact ionization, can be trapped in the gat

17、e oxide near the drain region where the channel electric fields are maximum. These trapped electrons attract positive charge to the oxide interface and shorten the effective channel length. Depending on the device sensitivity to short channel effects, the electron-trapping enhances the p-channel MOS

18、FET drive current, increases the channel mobility and transconductance, and decreases the absolute magnitude of the threshold voltage with consequent increase in off-state current. In advanced submicron CMOS technologies (gate length 0.25 m, gate oxide thickness 20- 30 Angstroms), the p-channel devi

19、ces hot-carrier-induced damage has been observed to be dominated by hot-hole injection . This hot carrier degradation mechanism results in interface-state generation as well as positive fixed charge formation. P-MOSFET devices stressed under the hot-hole injection exhibit decreased p-channel MOSFET

20、drive current, decreased channel mobility and transconductance, and increased absolute magnitude of the threshold voltage. Both electron and hole injection can be a problem depending on the device operation in the circuit. The physical damage mechanism depends on the oxide thickness, vertical and ch

21、annel electric field as well as the injection conditions. Oxide (both positive and negative) charge and interface traps affect transistor performance in all operating regimes. Parameters such as threshold voltage, input and output transconductance, and drive currents are commonly monitored to identi

22、fy performance change. The rate of change of each parameter is determined by the MOSFET design and IC process details. Both p- and n-channel MOSFETs are affected by hot carriers. This document addresses only p-channel MOSFETs that are operating with a conducting channel. JEDEC Standard No. 60A -iv-

23、JEDEC Standard No. 60A Page 1 A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION UNDER DC STRESS (From JEDEC Board Ballot JCB-04-46, formulated under the cognizance of the JC-14.2.2 Subcommittee on Device Reliability Working Group 1 Scope The purpose of this document is to sp

24、ecify a minimum set of measurements so that valid comparisons can be made between different technologies, IC processes, and process variations in a simple, consistent and controlled way. The measurements specified should be viewed as a starting point in the characterization and benchmarking of the t

25、ransistor manufacturing process. In this document, change criteria are specified. However, these are to be used for comparison purposes only and should not be used as acceptance or rejection criteria. It is also important to realize that this procedure should not be interpreted as a means of predict

26、ing MOS IC failure rates. The impact of the p-channel MOSFET change on actual circuit performance is not addressed in this document. Though this procedure was developed for wafer level stressing, it is also applicable to packaged structures. The material contained in this publication was formulated

27、under the cognizance of the JEDEC 14.2 Committee. This document replaces JESD60 “A Procedure for Measuring p-channel MOSFET Hot-Carrier-Induced Degradation at Maximum Gate Current Under DC Stress.” 2 Applicable standards ASTM F616-86, Standard Method for Measuring MOSFET Drain Leakage Current. ASTM

28、F617-86, Standard Method for Measuring MOSFET Linear Threshold Voltage. ASTM F1096-87, Standard Method for Measuring MOSFET Saturated Threshold Voltage. JESD77-B, Terms, Definitions, and Letter Symbols for Discrete Semiconductor and Optoelectronic Devices. JESD28-1, A Procedure for Measuring N-Chann

29、el MOSFET Hot-Carrier Induced Degradation Under DC Stress. JEDEC Standard No. 60A Page 2 3 Terms and definitions 3.1 bulk current, dc (IB): The direct current into the bulk contact. 3.2 bulk-source voltage (VBS): The bulk-to-source voltage. 3.3 constant-current threshold voltage (VT(ci): The gate-so

30、urce voltage at which the drain current is equal to a constant current, appropriate for a given P-MOSFET technology, times the ratio of gate width (W) to gate length (L). VT(ci)can be calculated using =LWIIat VVDoDGST(ci)(1) where: W and L are the gate width and gate length as printed on the wafer;

31、IDois typically 0.025 A but another value may be selected for a given technology such that VT(ci) is in the subthreshold region of the device. NOTE 1 The measurement technique must determine VT(ci)to within a 1-mV resolution. If the VGSstep size is larger than 1 mV, then a linear interpolation metho

32、d may be used to achieve the 1-mV resolution. NOTE 2 Typical dc bias voltages for the linear VT(ci) measurements are VDS= VDS(lin)and VBS = VBB. For the saturation VT(ci) the measurements conditions are VDS= -VDDand VBS = VBB. VDD is the voltage at the external VDDterminal and asuumed to be positive

33、. 3.4 drain current, dc (ID): The direct current into the drain contact. 3.5 drain leakage current (ID(leak): The drain current when the transistor is biased in its off state. NOTE 1 ID(leak) may have contributions from channel off-state current, gate-induced drain leakage (GIDL), and drain-to-gate

34、tunneling currents. NOTE 2 Typical bias voltages for ID(leak)measurements are VDS= -VDDand VBS= VGS= VBB. VDD is the voltage at the external VDDterminal and asuumed to be positive. 3.6 drain-source voltage (VDS): The drain-to-source voltage. JEDEC Standard No. 60A Page 3 3 Terms and definitions (con

35、td) 3.7 extrapolated threshold voltage (VT(ext): The threshold voltage extrapolated from measurement of maximum slope (gm(max) of the ID-VGScurve, as described in ASTM F617-86. VT(ext) can be calculated using VV(g)I(g )gT(ext) GS m(max)D m(max)m(max)= (2) where: VGS(gm(max) is the gate voltage at th

36、e point of the maximum slope of the ID-VGScurve; ID(gm(max) is the drain current at the point of the maximum slope of the ID-VGScurve; gm(max)is the maximum slope of the ID-VGScurve in the linear region. NOTE The bias voltages for VT(ext) measurements are VDS= VDS(lin)and VBS = VBB. 3.8 gate current

37、, dc (IG): The direct current into the gate contact. 3.9 gate-source voltage (VGS): The gate-to-source voltage. 3.10 linear drain current (ID(lin): The drain current when the transistor is biased in the linear region. NOTE Typical bias voltages for ID(lin)measurements are VDS(lin)= -0.1 V, VGS= -VDD

38、, and VBS = VBB. VDD is the voltage at the external VDDterminal and asuumed to be positive. 3.11 linear drain voltage (VDS(lin): The drain-to-source voltage for linear region measurements. NOTE Typically, VDS(lin)= -0.1 V. 3.12 maximum linear transconductance (gm(max): The maximum slope of the ID-VG

39、Scurve in the linear region. NOTE 1 The gate voltage shall be varied in increments no greater than 20 mV from below the turn-on voltage to a value great enough to ensure that the maximum slope point has been reached. NOTE 2 The slope shall be calculated using a three-point linear least-squares best-

40、fit algorithm as defined in ASTM F617-86. NOTE 3 Typical bias voltages for gm(max)measurements are VDS= VDS(lin)and VBS= VBB. JEDEC Standard No. 60A Page 4 3 Terms and definitions (contd) 3.13 metal-oxide-semiconductor field-effect transistor (MOSFET): An insulated-gate field-effect transistor in wh

41、ich the insulating layer between each gate electrode and the channel is oxide material; the gate is metal or another highly conductive material. NOTE See JESD77-B for further clarification of MOSFET terms. 3.14 nominal bulk supply voltage (VBB): The nominal bulk voltage for a given technology. NOTE

42、Typical VBB= 0. If VBBis not equal to zero, then VBBfor a P-MOSFET is positive. 3.15 nominal power supply voltage (VDD): The nominal supply voltage for a given technology. NOTE VDDis positive. 3.16 punch-through voltage (VPT): The reverse-bias drain voltage applied to the drain terminal that results

43、 in significant drain-to-source current even though the transistor is biased in its off state. NOTE 1 Punch-through is differentiated from junction breakdown in that the current path is from drain to source instead of from drain to substrate, as is the case of junction breakdown. NOTE 2 Typical dc b

44、ias voltages for VPTmeasurements on p-channel MOSFET devices are VDSat ID= -1 A and VGS= VBS= VBB. 3.17 saturation drain current (ID(sat): The drain current when the transistor is biased in the saturation region. NOTE Typical bias voltages for ID(sat)measurements are VDS= VGS= -VDDand VBS= VBB. VDD

45、is the voltage at the external VDDterminal and asuumed to be positive. 3.18 time to target (ttar): The time it takes under specific conditions for the value of a particular parameter to change by a specified amount or to a specified value. NOTE For most parameters, a change of 10% from the unstresse

46、d value is often used. For threshold voltage, a 50 mV change is often used. No criterion is specified for the drain leakage current. These values have been arbitrarily chosen, and no relationship to circuit failure is implied. Other criteria (e.g., 5% change from the unstressed value) may be used fo

47、r a given technology. JEDEC Standard No. 60A Page 5 4 Technical requirements 4.1 Equipment requirements The measurement system must be capable of the simultaneous application of voltage and measurement of current at the gate, drain, and substrate contacts of the transistor. The system must be able t

48、o measure 100 pA with a resolution 1 pA or better. The voltage overshoot during parametric measurements and stress must not exceed 1% of the applied voltage. The measurement system must be capable of supplying the maximum stress current of the transistor. 4.2 Test structure requirements A p-channel

49、MOSFET fabricated on a n-type bulk substrate/well should be used. A minimum channel length of the process is recommended, but other channel lengths may also be used. Current drive should be small enough so that the stress does not raise the junction temperature more than 5 oC. The source, drain and gate contacts of the transistor must be contacted. The bulk shall be contacted or floating depending on the technology under inverstigation (e.g., silicon-on-insulator pMOSFETs can have floating n-wells). To minimize parasitic voltage drops between the applied d