JEDEC JESD52-1995 Description of Low Voltage TTL-Compatible CMOS Logic Devices《低电压晶体管的描述 兼容CMOS逻辑设备》.pdf

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1、O CD W -a _ EIA JESD52 75 I 3234600 0564377 340 - - - -= - Reproduced By GLOBAL - a ENGINEERING DOCUMENTS With The Permission of EIA f - - Under Royalty Agreement EINJEDEC STANDARD Standard for Description of Low Voltage TTL-Compatible CMOS Logic Devices EINJESD52 NOVEMBER 1995 ELECTRONIC INDUSTRIES

2、 ASSOCIATION ENGINEERING DEPARTMENT - EIA JESD52 95 3234b00 0.564380 Ob2 NOTICE EWJEDEC Standards and Publications contain material that has been prepared, progressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EM General Counsel. EIA/JEDEC

3、 Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchases, facilitating interchangeability and improvement of products, and assisting the purchaser is selecting and obtaining with minimum delay the proper product f

4、or his particular need. Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC from manufacturing or selling products not conforming to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EU members, wheth

5、er the standard is to be used either domestically or internationally. EINJEDEC Standards and Publications are adopted without regard to whether their adoption may involve patents or articles, materials, or processes. By such action, EWJEDEC does not assume any liability to any patent owner, nor does

6、 it assume any obligation whatever to parties adopting the EWJEDEC Standards or Publications. The information included in EWJEDEC Standards and Publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within th

7、e EWJEDEC organization there are procedures whereby an EWJEDEC Standard or Publication may be further processed and ultimately becomes an ANSEIA Standard. Inquiries, comments, and suggestions relative to the content of this EWJEDEC Standard or Publication should be addressed to the JEDEC Executive S

8、ecretary at EM Headquarters, 2500 Wilson Boulevard, Arlington, VA 2220 1. (From JEDEC Council ballot JCB-95-19, formulated under the Cognizance of JEDEC JC-40 Committee on Standardization of Digital Logic.) Published by OELECTRONIC INDUSTRIES ASSOCIATION 1995 Engineering Department 2500 Wilson Boule

9、vard Arlington, VA 2220 1 “Copyright“ does not apply to JEDEC member companies as they are free to duplicate this document in accordance with the latest revision of the JEDEC Publication 2 1 “Manual of Organization and Procedure“. PRICE: Please refer to the current Catalog of EIA, JEDEC, and TIA STA

10、NDARDS and ENGINEERING PUBLICATIONS or call Global Engineering Documents, USA and Canada (1-800-854-7179) International (303-397-7956) Printed in U.S.A. All rights reserved EINJEDEC STANDARD No. 52 STANDARD FOR DESCRIPTION OF LOW VOLTAGE TTLCOMPATIBLE CMOS LOGIC DEVICES CONTENTS Page 1 Interface sta

11、ndard 1.1 Purpose 1.2 Scope 2 Definitions 3 Standard specifications 3.1 Absolute maximum continuous ratings 3.2 Recommended operating conditions 3.3 DC specifications 3.4 Additional dynamic power supply characteristics 4 Test circuits and switching waveforms 5 Reference to other applicable JEDEC sta

12、ndards and publications 1 6 9 -1- EIA JESD52 95 3234600 0564383 871 H EINJEDEC STANDARD No. 52 -11- EIA JESD52 95 3234600 05b4384 708 EIMJEDEC STANDARD No. 52 Page 1 STANDARD FOR DESCRIPTION OF LOW VOLTAGE TTLCOMPATIBLE CMOS LOGIC DEVICES (From JEDEC Council Ballot JCB-95-19, formulated under the co

13、gnizance of JC-40 Committee on Standardization of Digital Logic.) 1 Interface standard 1.1 Purpose To provide a standard for low voltage CMOS logic series specifications for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. 1.2 Scope

14、 This standard defines dc interface and switching parameters for a high speed, low voltage CMOS digital logic family driving/driven by parts of the same family. This standard covers specifications for CMOS logic series as defined in section 2. 2 Definitions CMOS Series includes devices which utilize

15、 CMOS technology. Includes devices whose input logic levels are TTL-compatible. Compliant to JEDEC Standard No. 8-A. Prefixes: Prefixes “54“ or “74“ immediately preceding family name indicate the operating temperature range. For example, 54XXX refers to the military (MIL) version of devices which ar

16、e specified over the temperature range of -55 OC. to 125 OC. 74XXX refers to the commercial (COML) version of devices which are specified over -40 “C to 85 “C. EIA JESD52 95 m 3234600 0564385 644 m EINJEDEC STANDARD No. 52 Page 2 3 Standard specifications 3.1 Absolute maximum continuous ratings (Not

17、es 1 and 2) Supply voltage, VDD . -0.5 V to 4.6 V dc input voltage, VIN (except I/O pins) -0.5 V to 4.6 V dc output voltage, VOUT (including U0 pins)(Note 3) . -0.5 V to VDD + 0.5 V dc input diode current, IIK (VIVDD) +20 mA dc output diode current, IOK (Vo VDD) f 50 mA dc current into any output in

18、 the low state, IOL (Note 4) IOL(rated) dc current into any output in the high state, IOH (N 5) . IOH(rated) Storage temperature range 1 -65C to 150C NOTES 1 Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions b

19、eyond those indicated may adversely affect device reliability. Functional operation under absolute- maximum-rated conditions is not implied. - 2 Under transient conditions these ratings may be exceeded as defined in this specificaton. 3 Not to exceed 4.6 V. 4 Not to exceed 70 mA. 5 Not to exceed -35

20、 mA. EIA JESD52 95 m 3234600 05b43Bb 580 m EINJEDEC STANDARD No. 52 Page 3 3.2 Recommended operating conditions I Symbol I TA AtlAv Parameter I Min Supply voltage (Note 1) 2.7 Input voltage (Note 1) O Output voltage (Note 1) O I Operating fi-ee-air temperature Input transition rise or fall rate (Not

21、e 2) O NOTES 1 Unless otherwise specified. Max I Unit 3.6 I V 125 “C nsN 2 As measured between 0.8 V and 2 V. EIA JESD52 75 m 3234b00 05b4387 417 m Symbol Parameter 1, High-level input voltage OZ, IOZL IDD Off-state output current (Note 2) . Off-state output current (Note 2) . Static supply current

22、EINJEDEC STANDARD No. 52 Page 4 3.3 DC specifications Test conditions I 54/74 Series Unit Max I Min V 2 V Low-level input voltage I 0.8 V OH High-level output voltage V 0.2 V VOL Low-level output voltage 0.4 V a Input current A5 A15 10 -10 1.5 I I *IDD Static supply current per input at a specified

23、level 1 Vnn = MIN to MAX. I NOTES 1 Refer to manufacturers datasheets. 2 For I/O pins, Iom and Io= include the input leakage current. EIA JESD52 95 3234b00 05b4388 353 Min EINJEDEC STANDARD No. 52 Page 5 Max 3.4 Additional dynamic power supply characteristics Total Power Supply Current ID I Svmbol I

24、 Parameter I Test conditions I 54/74 Series I I (Note 3) mA I I IpmI ynamic Power supply current I VDD = MAX, outputs open and enabled (Note 2) NOTES 1 Q, ID. and C, are additional recommended parameters for specing power supply characteristics. See individual manufacturers datasheets. 2 QD value is

25、 intended to give an estimate of the dynamic power supply current component in the equation for the total power supply current (ID). QD should be measured by switching the input(s) under test from rail to rail. Ail other inputs should be held at VDD or GND to exclude any static. power supply compone

26、nt such as A ID, om the measurement. If the devices are tested at a sufficiently high frequency, the dc supply cment will contribute a negligible amount to the overall power consumption and can therefore be ignored. If, for example, the power consumption is measured at 10 Mhz under the conditions st

27、ated above, the following formula is used to determine the devices QD value: QD(hII+) = Measurement Power Supply Current/lO (Mhz) - C, VDD where C, VDD represents the contribution of load capacitance to the dynamic power dissipation and C, = Load capacitance (i.e., tester, fixture, socket, etc. ) in

28、 pF. AIDD = Power supply current for a logic high input (VDD - 0.6 V) D, = Duty Cycle for each switching input NT = Number of switching inputs QD = Dynamic charge moved by an input pulse (” or LHL) fq = Equivalent frequency of operation No = Number of outputs switching EIA JESD52 95 m 3234600 05b438

29、9 2T m Test EINJEDEC STANDARD No. 52 Page 6 Switch All currents are in milliamperes and all frequencies are in Mhz PLH tPHL The operating conditions should be explicitly stated for each device and a corresponding operating frequency (such as CLOCK rate) should be used as a reference. Open open 3 Act

30、ual values of ID are optional. If present, it is recommended that an equivalent frequency of 10 Mhz be used in the equation. 4 C, in pF is calculated from QD measurements by using the formula: where QD is expressed in pAh4Hz and VDD is expressed in volts. 4 Test circuits and switching waveforms VOO

31、I Pulse Generator CL = 50 pF or equivalent (includes jig and probe capacitance). RL = R, = 500 z or equivalent. Optional values of R, = RL = 1 KQ may be used for devices with output drive currents s 8 mA. 2 tPHZ GND I I tPLZ 6V RT = Zorn of pulse generator (typically 50 Q). EIA JESD52 95 3234b00 056

32、4390 TO1 H EINJEDEC STANDARD No. 52 Page 7 Propagation delay measurements Pulse duration (width) measurements High-level Input Pulse Low-level Input Pulse Output requirements: Device must follow tnAh table VOL I VOL max VOH 2 VOH min tr = tf = 2.5 ns (or as fast as required) from 10% to 90% of O V t

33、o 2.7 V. Input Conditions: EIA JESD52 95 3234600 0564393 9L18 EINJEDEC STANDARD No. 52 Page 8 Setup and hold time measurements Asynchronous Control Synchronous Cod Enable Input Wut High-2 to LOW Enable time measurements EIA JESD52 95 3234600 0564392 884 EIALTEDEC STANDARD No. 52 Page 9 Disable time measurements 5 Reference to other applicable JEDEC standards and publications JEDEC Standard NO. 8-A “Interface Standard for Nominal 3 Vi3.3 V Supply Digital Integrated circuits