JEDEC JESD51-8-1999 Integrated Circuit Thermal Test Method Environmental Conditions - Junction-to-Board《集成电路热测试方法环境条件－Junction-to-Board》.pdf

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1、JEDEC STANDARD Integrated Circuit Thermal Test Method Environmental Conditions - .Ji_inc,t!nn-tn-Roa-d JESD51-8 OCTOBER 1999 ELECTRONIC INDUSTRIES ALLIANCE JEDEC Solid State Technology Association Dcctrd+ industrie CSJlknse NOTICE EIAIJEDEC standards and publications contain material that has been p

2、repared, reviewed, and approved though the JEDEC Board of Directors level and subsequently reviewed and approved by the EIA General Counsel. EINJEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facil

3、itating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. EIAIJEDEC standards and publicati

4、ons are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the EWJEDEC standards or publications. The

5、information included in EWJEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer standard or publication may be further processed and ultimately become an ANSUEL4 standard. vicwyuini. Withifi the JED

6、EC gaiiizatiii there ae prcedies Eheebr ii EM/JEDEC No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this EWJEDEC standard or publication should be addressed to JEDEC

7、Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA 22201-3834, (703)907-7560/7559 or www.jedec.org Published by ELECTRONIC INDUSTRIES ALLIANCE 1999 Engineering Department 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge, however ELA

8、retains the copyright on this material. By downloading this file the individual agrees not to charge or resell the resulting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications or call Global Engineering Documents, USA and Canada (1-800-854-7179), Int

9、ernational (303-397-7956) Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the Electronic Industries Alliance and may not be reproduced without permission. Organizations mq- usually applicable to semiconductor devices using a forward biased temp

10、erature sensitive parameter. JEDEC Standard No. 5 1-8 Page 6 5.3 Determination using Kractor The junction-to-board thermal resistance can then be determined by equation (3): where TBO = TSS = Initial board temperature before heating power is applied Final board temperature when steady state has been

11、 reached. 5.4 Calibration equation A calibration equation may also be used to determine the junction temperature as specified in reference Pl. 6 Test Procedure Prior to making actual thermal measurements, the temperature-sensitive parameter shall be empirically calibrated using the procedure in sect

12、ion 3.3 of the reference 2. 6.2 Thermal equilibrium Place the package and test board in the ring cold plate. Prior to recording the initial conditions of the thermal test, verify that the device has reached a state of equilibrium with the ambient temperature. To verify that stabilization has occurre

13、d, wait an initial 5 minutes minimum, then record the TSP, wait an additional 5 minutes and record a second TSP. If ATj as determined by the TSP measurement is less than or equal to 0.2 OC, then equilibrium has been achieved. If equilibrium has not occurred, then continue for additional 5 minute int

14、ervals. 6.3 Initial readings After equilibrium has been reached, record the values for the TSP and the initial board temperature TO, 6.4 Apply power The power levels shall be chosen such that the junction temperature rise during testing is between 15 “C and 30 “C. Apply the heating voltage (VH) and

15、the heating current (IH) to the device. 6.5 Steady state For a test measurement to be completed, verification that thermal steady state has been reached shall be done before the final readings can be taken. Steady-state shall be determined as required in section 3.6 of reference 2. JEDEC Standard No

16、. 5 1 -S Page 7 6.6 Steady state measurements After a steady-state has been reached, record the values for the TSP, the heater voltage (VE,), the heater current (IH), the time required to reach steady state (tHss), and the final board temperature at the end of the test (TBs,). 7 Usage 7.1 Thermal si

17、mulation models The junction-to-board thermal resistance, ROJB, will find use as an indicator of thermal performance for incorporation into board level thermal simulation models. How the information is used in a board level simulation and the resulting accuracy will depend on the simulation software

18、. Since ReJB is primarily a figure of merit, the resulting accuracy of the board level simulations will be less than could be obtained with a more detailed model. 7.2 Simulation validation Another use of ReJB will be the validation of package simulation models by providing defined boundary condition

19、s for simulation. Since the thermal test board can contribute up to 50% of the thermal resistance measured in this test, it is required that the test board be accurately modeled. Actual physical measurements of the test board are needed for accurate models. The junction-to-board determined by this s

20、pecification must not be confused with similar measurements obtained with the “double cold plate” apparatus. 7.3 YJB junction-to-board thermal characterization parameter Junction-to-board thermal resistance, ReJB, must not be confused with a junction-to-board thermal characterization parameter, Y JB

21、, determined using the methods specified in “Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)”. Frequently, the junction-to- board thermal resistance will be larger than junction-to-board thermal characterization parameter. JEDEC Standard No. 5 1 -S Pa

22、ge S 8 Test conditions to be reported The values listed in table 1, which are needed to describe this test and the results, must be reported when publishing. Table Environmental I Measurements - Thermal measurement test conditions and data Darameters Condition Parameters 1 Data Parameters and Result

23、s I Device Identification Date Cold Plate Drawing number Test Board Specification (and drawing number) Thermocouple Type and gauge rhennocouple attachment location TBO (“cl JEDEC Standard No. 5 1-8 Page 9 PLUG 65.0 - 69.0 - 63.0 INLET 45.0 - ounm Annex A - Ring cold plate design example DRILL AND TA

24、P 12 PL -_ - 0 I DRILL 6 mm TW.8PL . / DRILL 6 mrn BLIND HOLE TAP , , - 0.0 25,0 21.0 - PLUG 6.0 - , 99 ou , I 1 ji I i i j I? I - 0 / 104.0 - 98.2 - 6.0 - 0, THREADED HOLES 5 PL FOR EACH BOARD SIZE ,FOR ALIGNMENT POST LUG THREADED HOLES FOR CLAMP, 2 PL PLUG I h THROUGH HOLE II m BLIND HOLE x Figure

25、 Ala - Drawing of boiiom piece of ring cold plate fixture designed for packages with footprint less Ihan 30 mrn in longest dimension. Fabricated from copper and then nickel plated. All dimensions are basic. If 8-32 screws are used instead of M4 to center the teSI board, threaded hdes should be moved

26、 0.1 mm furiher from the center line of the fixture. Only the externally visible dnlled holes are shown in side views CLEARANCE HOLES FOR ALIGNMENT POST 5 PL FOR EACH BOARD SIZE PLI CLEARANCE HOLES FOR CLAMP. 2 PL PLL DRILL 4.5 rnm i2 PL PLUG - 104.0 PLUG R3 O I 0 - - 85.5 1 PLUG O Y) O I o 16.0 12.

27、0 60- 00- f I 9 O o o 2 BLINDHOLE THROUGHHOLE DRILL 6 rnm DRILL 6rnm BLIND HOLE TAP 54.0 36.0 0.0 - ili I , Figure Alb - Drawing of top piece of the nng cold plate fixture designed for packages wth fwtpnnt less than 30 rnrn in longest dimension. Top piece is shown upside down for easy of documenting

28、 dimensions. Refer to figure 1 to illustrate assembly. Fabncated from copper and then nickel plated. All dimensions are basic. Only externally visible dnlled holes are shown in side views. JEDEC Standard No. 51-S Page 10 Annex A - Ring cold plate design example ORILL AND TAP 7 PL DRILL 6 mm TAP, 8 P

29、L. / ORILL 6 mrn BLIND HOL: TAP /c;loo25) q 90 - O0 O ID 106.00 - 100.2 - 94.0 - PLUG 82.0 - 78.0 - INLE- 470 - OUTLE 18.0 - 16.0 - 12.0 - PLUG 0.0 - PLL i -0 I I / M4 6 O m N O IG I j o -I- -1- - - - i l i I I I i l I 10 -I- -I- - I PLUG YI 3, .- THREADED HOLES IFOR ALIGNMENT POST 5 PL LUG THREADED

30、 HOLES FOR CLAMP. 2 PL ?LUG 16.0 12.0 -3 1; I l I I 6.0 I 0.0 - I O O o N g THROUGH HOLE BLINDHOLE Figure A2a - Drawing of bottom piece of ring cold plaie fixture designed for packages on 101.6 mm test board. Fabricated from copper and then nickel plaled. All dimensions are basic. Only lhe externall

31、y visible drilled holes are shown in ihe side views. CLEARANCE HOLES FOR ALIGNMENT POST 5 PL DRILL 4.5 mm 7 PL 1060 - 1002 - 940 - PLUG 820 - 780 - CLEARANCE HOLES FORCLAMP.?_PL , 470 - e 0 160 - 12 o PLU O0 - PLUG 1. PLUG o -0 I / O O lomsr 85.0 - LUG Outlel 56.0 - Inlet 38.0 90 - 00- PLUG 1 DRILL

32、6 mm TAP. 8 PL DRILL 6 rnm 3 TAP BLIND HOLE 3 O0 IDO 120 -I I I k-Q 60 - O0 o o ,“ O N THROUGH HOLE n BLINDHOLE Figure A2b - Drawing of top piece of nng cold plate fixture designed for packages on 101 .S rnrn test board. Fabricaied from copper and then nickel plated. All dimensions are basic. Only externally visible dnlled holes are shown in lhe side views.