JEDEC JEP172A-2015 Discontinuing Use of the Machine Model for Device ESD Qualification.pdf

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1、JEDEC PUBLICATION Discontinuing Use of the Machine Model for Device ESD Qualification JEP172A (Revision of JEP172, July 2014 JULY 2015 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Bo

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8、e individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technol

9、ogy Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Publication No. 172A -i- DISCONTINUING USE OF THE MACHINE MODEL FOR DEVICE ESD QUALIFICATION Contents 1 Scope 1 2 References 1 3 Terms, Def

10、initions, and Letter Symbols 2 4 Background 3 5 MM vs. HBM and CDM 4 6 Metal Discharge versus CDM Discharge . 6 7 Field Data Analysis 9 8 Standards Bodies and Positions on MM. 9 9 Conclusions 10 10 Epilogue . 10 11 Common Goals . 10 Annex A Differences between JEP172A and JEP172 10 JEDEC Publication

11、 No. 172A -iii- Foreword The machine model test, as a requirement for component ESD qualification, is being rapidly discontinued across the industry. This publication is intended to document why MM evaluation is not necessary for qualification. The following major conclusions can be made about MM in

12、 general: MM is redundant to HBM at the device level since it produces the same failure mechanisms, and the two models generally track each other in robustness and in failure modes produced. The MM test has more variability and, consequently, less repeatability than HBM due to the MMs greater sensit

13、ivity to parasitic effects in the tester circuitry. There are no significant engineering studies (with verified data) which could be used to establish a required passing level for MM. The test method was incorrectly given the name “machine model”, though no firm, unique connection between the model

14、and actual machine-induced device failures was ever established. In fact the model was developed as a “low-voltage HBM”. CDM does a better job of screening for fast metal-to-metal contact events than MM. The vast majority ( 99%) of electrical failures in manufacturing correlate to CDM or to EOS and

15、not to MM. MM testing has not shown any additional failures not explained by CDM, HBM or EOS. MM testing consumes resources and creates time-to-market delays while providing no additional failure modes or protection strategies which have not been covered by HBM and CDM. It is important to understand

16、 the scope of this memorandum. It summarizes what has been learned about the test method only. The information summarized here in no way diminishes the importance of proper grounding of any metal which may come in contact with ESD-sensitive devices or the importance of avoiding hard metal-to-metal d

17、ischarges. JEDEC Publication No. 172A Page 1 DISCONTINUING USE OF THE MACHINE MODEL FOR DEVICE ESD QUALIFICATION (From Board Ballot JCB-14-27, formulated under the cognizance of the JC-14.3 Subcommittee on Silicon Devices Reliability Qualifications and Monitoring.) 1 Scope Over the last several deca

18、des the so called “machine model“ (aka MM) and its application to the required ESD component qualification has been grossly misunderstood. The scope of this JEDEC document is to present evidence to discontinue use of this particular model stress test without incurring any reduction in the IC compone

19、nts ESD reliability for manufacturing. In this regard, the documents purpose is to provide the necessary technical arguments for strongly recommending no further use of this model for IC qualification. The published document should be used as a reference to propagate this message throughout the indu

20、stry. 2 References 1 JEDEC JESD47 “Stress-Test-Driven Qualification of Integrated Circuits”, www.jedec.org 2 JEDEC JESD22-A115 “Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM)”, www.jedec.org 3 ANSI/ESD STM5.2-2012 “Machine Model (MM) Component Level “ www.esda.org 4 M. Tanaka,

21、JEITA/JEDEC Meetings, Tokyo, September 2011. 5 M. Tanaka, K. Okada, and M. Sakimoto, “Clarification of Ultra-high-speed Electrostatic Discharge and Unification of Discharge Model,” EOS/ESD Symposium, pp, 170-181, 1994. 6 Industry Council on ESD Target Levels, “White Paper 1: A Case for Lowering Comp

22、onent Level HBM/MM ESD Specifications and Requirements,” August 2007, at www.esda.org or JEDEC publication JEP155, “Recommended ESD Target Levels for HBM/MM Qualification”, www.jedec.org 7 ANSI/ESD S20.20 - For the Development of an Electrostatic Discharge Control Program 8 ESDA standards document d

23、efinitions and hierarchy are summarized at www.esda.org/Documents.html JEDEC Publication No. 172A Page 2 3 Terms, Definitions, and Letter Symbols AEC Automotive Electronics Council ANSI American National Standards Institute CDM charged-device model EOS electrical overstress EPA ESD protected area ES

24、D electrostatic discharge ESDA Electrostatic Discharge Association; ESD Association FAR failure analysis report HBM human body model IC integrated circuit JEDEC JEDEC Solid State Technology Association JEITA Japan Electronics and Information Technology Industries Association MM machine model OEM ori

25、ginal equipment manufacturer STM standard test method JEDEC Publication No. 172A Page 3 4 Background As will be explained below, the machine model (MM) is a widely misunderstood component ESD qualification test method. It continues to generate confusion for both OEM customers and their IC suppliers

26、during ESD qualification. Many companies and design organizations continue to use MM, mostly as a legacy “required” practice, despite the fact that it has been downgraded by three standards bodies and is no longer recommended for qualification testing in accordance with JEDEC JESD47 1. The automotiv

27、e industry, a longtime user of this method, no longer requires it in their AEC-Q100 list of qualification tests. The scopes of the JEDEC (JESD22-A115) 2 and ESDA (ANSI/ESD STM5.2) 3 test method documents have also been changed to reflect this status. There are a number of reasons for these changes,

28、as will be outlined below. The continued use of MM for qualification based solely on legacy requirements has no technical merit given the information that has been gathered over the last few years. Those companies who continue to use MM will take on an unnecessary and burdensome business approach wi

29、thout any technical benefit. The reasons against use of the MM are as follows: 1) Historically speaking, the 200 pF, “0 ohm” model, which later became known as the machine model, originated from several Japanese semiconductor corporations as a worst-case representation of the Human Body Model (HBM).

30、 The model was later presumed by some, because of the lower discharge impedance, to simulate abrupt discharge events caused by contact with equipment and empty sockets (functional test, burn-in, reliability testing, pick and place operations, etc). This happened at a time when the very fast rise tim

31、e of metal-metal discharges was not well-understood. Since that time, the Charged Device Model (CDM) has been proven to quite adequately cover these events. 2) Recently, M. Tanaka-san (Renesas Electronics) at the September 2011 JEITA meetings 4 presented rationale and data supporting the elimination

32、 of the MM test. According to his historical account, the so-called Machine Model originated at Hitachi (now Renesas Electronics) about 45 years ago and was introduced to Japanese semiconductor customers as a test case to represent the HBM test in their IC product test report. This test method sprea

33、d widely to the Japanese customer base and was later established as an ESD test standard by the EIAJ in 1981. Around 1985 and onwards, some began to mistakenly refer to the test as the Machine Model. Then, starting in 1991, ESDA, JEDEC and IEC adopted the model and its name as a new test standard. A

34、s use of the model increased, it was realized that the Machine Model name caused a lot of misunderstanding that needed to be clarified. 3) In the early days of ESD device testing there was also a desire to avoid the high pre-charging voltages of the HBM test (2 kV and higher), and the 200 pF and low

35、 impedance of the “MM” was thought to be an equivalent but safe lower voltage test to address the same failure mechanisms as HBM. However, establishment of a single translation from MM voltage to HBM voltage has been difficult to achieve. Protection design has traditionally been focused on meeting t

36、he HBM requirement, but MM testers are susceptible to parasitic circuit elements, with these parasitics from relay switching networks in the simulators causing more variation in the MM waveform than waveforms from HBM testers. In spite of this and without any supporting data, 200 V MM became establi

37、shed as a de facto requirement. It was thought to be the safe level for handling and that this level had to be simultaneously met along with the de facto 2 kV HBM standard. In reality a device with a 2 kV HBM withstand voltage might have an MM withstand voltage anywhere from 100 to 300 V, depending

38、on the device characteristics and the MM tester parasitics. This led to much of the confusion associated with specifying both HBM and MM levels. JEDEC Publication No. 172A Page 4 4 Background (contd) The next important reason for discontinuing MM is that fast discharges to or from a metal surface ar

39、e not correctly represented by the MM. The characteristics of the MM rising pulse were not established based on comparison of measurements on machine pulses, but rather were determined by characteristics of the already developed HBM simulators. The fast rising leading edge of metal-to-metal discharg

40、es are actually more effectively simulated using the current standard CDM test methods. This is known today because of the development of high speed oscilloscopes. However, during the 1980s, there was a misunderstanding that MM was a good representation for CDM. This misunderstanding actually delaye

41、d the eventual development and acceptance of the CDM standards used today. Later in the 1990s, with the much improved and accurate test for CDM and with the wider recognition that the fast discharges are covered by CDM alone, the test for MM became more frequently replaced by CDM. 5 MM vs. HBM and C

42、DM The waveforms for HBM, MM and CDM are compared in Figure 1. The HBM and MM have similar ranges of rise time (2-10 ns). Therefore, any thermal heating in silicon taking place in this time period leads to the same failure mechanisms for both models. This holds true for all technologies, including a

43、dvanced technology nodes. This early part of the waveform determines where and how protection circuits must be deployed in design. With similar rise time characteristics, HBM and MM encourage the same protection designs. For CDM, on the other hand, the rise time is much faster (0.1 0.5 ns) and often

44、 leads to a unique failure mechanism, like oxide breakdown. Even more important, the observed ESD field failures are dominated by oxide breakdown when the CDM level is not adequate. Thus, a different set of protection strategies are generally needed for CDM. This makes it even more critical to focus

45、 on CDM qualification, instead of duplicating the HBM test information by using the MM. In Figure 1, we also show the observed failure modes for the same I/O pin after stressing with HBM, MM and CDM. It is clear that, with HBM and MM, the damage sites were the same, occurring in the protection diode

46、. However, with CDM stress, the damage site corresponds to oxide breakdown in the output transistor. This also illustrates the fact that meeting high levels of MM does not improve the CDM performance until the right effective design techniques are employed. JEDEC Publication No. 172A Page 5 5 MM vs.

47、 HBM and CDM (contd) Figure 1 Comparison of HBM, MM and CDM Waveforms Commercial MM testers have inductors built into the MM stimulus circuit. These inductors must be present to produce the oscillatory waveform required in the MM test method. The inductors, however, actually slow down the MM wavefor

48、m (Figure 1), and, therefore, MM cannot represent very fast metal-to-metal contact discharge as CDM does. On the other hand, the CDM test is directly represented by elevating the package potential and directly grounding the pin to produce the fast discharge. MM cannot be relied on to accurately mode

49、l fast metal-to-metal contact discharges, which are known to occur in the field. 3.5kV HBM 230V MM20 40 6080100Time (ns)Current (A)5.02.51.253.75MM = 200VHBM = 2kVCDM = 300V (typical)Similar rise times (10ns) for HBM / MM cause comparable rates of thermal (Joule) heating that result in similar observed fail mode500V CDMHBM and MM with very similar rise times produced the same failure damage mode as shown here in the protection diode of the I/O pinBut for the same I/O pin the CDM damage was in the output transistor Drain-Gate edgeJEDEC P