JEDEC JEP001A-2014 FOUNDRY PROCESS QUALIFICATION GUIDELINES (Wafer Fabrication Manufacturing Sites).pdf

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1、JEDEC PUBLICATION FOUNDRY PROCESS QUALIFICATION GUIDELINES (Wafer Fabrication Manufacturing Sites) JEP001A (Revision of JP001.01, May 2004) FEBRUARY 2014 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION FABLESS SEMICONDUCTOR ASSOCIATION NOTICE JEDEC standards and publications contain material that has been

2、prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facili

3、tating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications a

4、re adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The informa

5、tion included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed

6、and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address

7、 below, or refer to www.jedec.org under Standards and Documents for alternative contact information. Published by JEDEC Solid State Technology Association 2014 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the co

8、pyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission

9、. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC/FSA Joint Publication No. 001A -i- FOUNDRY PROCESS QUALIFICATION GUIDELINES (Wafer Fab

10、rication Manufacturing Sites) Contents Page Foreword iiIntroduction iiAcronyms ii1 Scope 12 Quality system 13 Responsibilities 13.1 Level 1 qualification 13.2 Level 2 qualification 24 Sample size 25 Use of packages 26 Reference documents 36.1 Industry standard documents 36.2 Selected references 57 Q

11、ualification test summary table 68 Interconnect reliability 78.1 Electromigration 78.2 Stress migration 98.3 Thermal cycling (copper interconnect) 118.4 Inter/intra-metal dielectric integrity 129 Conducting channel hot carrier injection (HCI) 139.1 DC conducting channel hot channel carrier (HCI) 131

12、0 Gate oxide integrity (GOI) 1610.1 Voltage ramp dielectric breakdown (V-RAMP) and charge to breakdown (QBD) 1610.2 Time-dependent dielectric breakdown (TDDB) 1810.3 Plasma process-induced damage (P2ID) 2111 Threshold voltage stability 2311.1 Ionic contamination bias temperature stress 2311.2 Ionic

13、contamination triangular voltage sweep 2411.3 Bias temperature instability in MOS devices (BTI) 2512 Technology qualification vehicle (TQV) tests 2612.1 Long term life test 2612.2 Early life test 2912.3 Temperature cycling test 3212.4 Temperature-humidity-bias (THB) / highly accelerated stress test

14、(HAST) 3312.5 Yield data and defect density calculation 3412.6 ESD characterization 3512.7 Latch-up characterization 3613 Process control monitor (PCM) characterization 3713.1 PCM data 3714 Construction analysis 4014.1 Construction analysis 40JEDEC/FSA Joint Publication No. 001A -ii- Foreword The do

15、cument provides methodologies for the minimum set of measurements to qualify a new semiconductor wafer process. It is written with particular reference to a generic silicon based CMOS logic technology. While it may be applicable to other technologies (e.g., analog CMOS, bipolar, BICMOS, GaAs, etc.),

16、 some sections apply specifically to CMOS. No effort was made in the present document to cover all the qualification requirements for specific other technologies, e.g., Cu/Low K interconnects or ultra-thin gate oxide. Any qualification requirements beyond the minimum set are to be developed for the

17、specific performance expected of the technology. The minimum set of measurements and the requirements for the qualification based on those measurements are to be determined between the foundry and its customers on an individual basis The process technology owner (foundry) will be required to documen

18、t the details of specific testing unique to the process being qualified. The guideline documents attempts to reflect common best practices in the semiconductor industry and updated in accordance to advancement in the semiconductor industry and JEDEC bylaws of periodic reviews. Introduction This publ

19、ication, entitled Foundry Process Qualification Guidelines, is co-sponsored by JEDEC and the FSA (Fabless Semiconductor Association). It originated at the FSA as a technology specific document, and has evolved into a generic set of qualification methodologies. The JEDEC sponsoring committee is JC-14

20、 through its JC-14.2 subcommittee on wafer level reliability. This document encompasses and references a number of other standards and procedures, some of which are in a state of constant revision and update. While a case might be made for producing a lean, concise guideline that does not spell out

21、specific procedures or requirements, the proposition of spelling out the essence of a comprehensive set of methodologies in one place has a practical value that outweighs the case for simplicity.(comment : the requirements are only spelled out in a number of cases. Best to be consistent and let the

22、existing JEDEC specs speak for themselves) Acronyms The following acronyms have been used in this document. BTS: bias temperature stress MM: machine model CDM: charged device model NBTI: negative bias temperature instability EFR: early failure rate P2ID: plasma-process induced damage EM: electromigr

23、ation PCM: process control monitor ESD: electrostatic discharge QBD: Charge to breakdown FA: failure analysis SM: stress migration/voiding FIT: Failures in time TC: temperature cycling GOI: gate oxide integrity TDDB: time-dependent dielectric breakdown HAST: highly-accelerated stress test THB: tempe

24、rature-humidity bias HBM: human body model TQV: technology qualification vehicle HCI: hot carrier integrity TVS: triangular voltage sweep HTOL: high temperature operating life VRDB: voltage ramp dielectric breakdown IMD: inter/intra-metal dielectric WLR: wafer level reliability JEDEC/FSA Joint Publi

25、cation No. 001A Page 1 FOUNDRY PROCESS QUALIFICATION GUIDELINES (Wafer Fabrication Manufacturing Sites) (From JEDEC Board Ballot JCB-14-04, formulated under the co-sponsorship of the JC-14.2 Subcommittee on Wafer Level Reliability, and the Fabless Semiconductor Associations Committee on Standard Fou

26、ndry Process Qualification (SFPQ) 1 Scope This document describes test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDE

27、C, such as JESD47, or other widely accepted standards for requirements documentation. There are two levels of qualification described. Level 1 is a pure process qualification intended to find reliability weaknesses. It primarily addresses technology wearout mechanisms through package or wafer level

28、reliability tests on specially designed test structures. Level 2 demonstrates the reliability of the process that corresponds to the reliability demands from projected or known applications. Level 2 testing can be implemented via the testing of a relevant functional technology qualification vehicle

29、(TQV), including life test. The level 2 tests are described in clause 12. Other Reporting requirements (e.g., PCM data) are also included. 2 Quality system It is the responsibility of the foundry to have the appropriate quality system in place with special emphasis on issues relating to equipment ca

30、pability, maintenance and calibration, continuous improvement and process control. In particular, a functioning SPC methodology should be demonstrated for all key processes (see EIA/JEDEC EIA-557A). As a minimum the foundry will have ISO9001 certification. The ISO9001 audit results by a third party

31、and subsequent corrective actions on deficiencies shall be made available to the customer upon request. For those supplying to automotive applications, the foundry may also have to demonstrate requirements from TS 16949 standard to meet the needs of these products 3 Responsibilities 3.1 Level 1 qual

32、ification The foundry is responsible for the design and implementation of the level 1 test vehicle (i.e. TESTCHIP). For the special case of a foundry customer driving process development, development of the level 1 test vehicle may be shouldered in whole or in part by the customer. The foundry shall

33、 fabricate the qualification silicon, execute the described level 1 tests and create the qualification report. The tests and qualification report may be done by the foundry or third party test vendor. The qualification requirements may be reduced for a derivative process, where the parent process ha

34、s already been fully qualified at the same location. JEDEC/FSA Joint Publication No. 001A Page 2 3.2 Level 2 qualification In general, the foundry is responsible for the design and implementation of the Level 2 test vehicle (e.g., SRAM or pilot product). For the special case of a foundry customer dr

35、iving process development, or where the customer requires TQV data before such a vehicle becomes available, development of the Level 2 test vehicle may be shouldered in whole or in part by the customer. The foundry, customer or third party test vendor may execute the Level 2 (TQV) tests and requisit

36、e failure analysis. The foundry will be responsible for suggesting and implementing corrective action based on the failure analysis results. The qualification report shall adhere to the minimum reporting requirements and format described in this document. While it is expected that a particular found

37、ry methodology may differ from the methods outlined in this document, the wafer foundry should demonstrate to the customer that it has satisfactorily addressed all issues of interest. The wafer foundry should therefore provide a documented procedure and supporting data that provide an assessment of

38、potential failure and wearout mechanisms. 3.3 Reporting Requirements Specific reporting requirements are included for the tests catalogued in this document. General reporting requirements include appropriate signoff, archiving and revision control, and the inclusion of supporting documents as approp

39、riate. The Level 1 qualification report shall include: (1) qualification plan, (2) description of the test vehicle including relevant test structure features and dimensions, (3) summary of test methods used, (4) pass/fail criteria, and (5) test results, analysis and model parameters as described in

40、this document. The Level 2 qualification report shall include: (1) qualification plan, (2) description of the technology qualification vehicle (TQV), (3) test description and specification, (4) pass/fail criteria (5) test results and analysis including failure rates, and (6) FA results. 4 Sample siz

41、e In general, data should come from 3 non-consecutive wafer lots, although the use of more lots is not precluded. A wafer lot is a group of wafers processed as a batch through the same or matched equipment in the same processing interval, using the same or matched conditions, materials, and methods.

42、 Typical sample sizes per lot are given in the individual test descriptions. Where applicable, confidence limits for each test population should be calculated. A conservative estimate of 40 die per wafer was made in determining sample size for tests that required the usage of all dies on the wafer.

43、5 Use of packages Packages with a wire-bonded die that are capable of higher temperatures are generally used for testing of the technology qualification vehicle (TQV) or pilot product. A qualification report for the standard wire-bonding process should be included. Advanced packaging (e.g., BGA, fli

44、p-chip or chip-scale) may be substituted where applicable. This, in combination with TC and THB tests will demonstrate the assembly capability of this wafer fab process. Side brazed ceramic packages are generally required for process wear-out tests performed at package-level at Temperatures greater

45、than 155 C. Consequently, wafer level testing is recommended wherever possible. All references to temperature in the following sections imply junction temperature unless otherwise specified. JEDEC/FSA Joint Publication No. 001A Page 3 6 Reference documents 6.1 Industry standard documents The followi

46、ng reference documents contain provisions that, through reference in this text, constitute provisions of this document. For dated references, subsequent amendments to, or revisions of, any of these publications do not apply. However, parties to agreements based in this publication are encouraged to

47、investigate the possibility of applying the most recent editions of the reference documents indicated. For undated references, the latest editions of the reference document referred to applies. Check the JEDEC website at http:/www.jedec.org. 6.1.1 Reliability assessment methodology JEDEC JEP70, Qual

48、ity and Reliability Standards and Publications. JEDEC JEP132, Process Characterization Guidelines. JEDEC JEP143, Solid State Reliability Assessment and Qualification Methodologies. JEDEC JEP122, Failure Mechanisms and Models for Silicon Semiconductor Devices. JEDEC JESD91, Method for Developing Acce

49、leration Models for Electronic Component Failure Mechanisms. JEDEC JESD94, Application Specific Qualification Using Knowledge Based Test Methodology JEDEC JESD659, Failure-Mechanism-Driven Reliability Monitoring. JEDEC JEP131, Process Failure Mode and Effects Analysis (FMEA). 6.1.2 Electromigration, stress migration, and IMD dielectric integrity ASTM F1260M-96, Standard Test Method for Estimating Electromigration Median Time-To-Failure and Sigma of Integrated Circuit Metallization. JEDEC JESD33, Standard Method for Measuring and Using the Temperature Coefficient of Resista